Mesa (master): intel/isl/icl: Use halign 8 instead of 4 hw workaround
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Thu Oct 3 17:44:53 UTC 2019
Module: Mesa
Branch: master
Commit: 0d606211014ddedc0eafedda53763651060b2279
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0d606211014ddedc0eafedda53763651060b2279
Author: Anuj Phogat <anuj.phogat at intel.com>
Date: Mon Oct 29 14:38:58 2018 +0200
intel/isl/icl: Use halign 8 instead of 4 hw workaround
v1 by Topi Pohjolainen
v2,v3 by Anuj Phogat:
- Apply for gen >= 11
- Remove wa_bug_xxx function
- Use helper functions
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
---
src/intel/isl/isl_gen8.c | 29 +++++++++++++++++++++--------
1 file changed, 21 insertions(+), 8 deletions(-)
diff --git a/src/intel/isl/isl_gen8.c b/src/intel/isl/isl_gen8.c
index 2199b8d22db..fe6166fc4ea 100644
--- a/src/intel/isl/isl_gen8.c
+++ b/src/intel/isl/isl_gen8.c
@@ -151,7 +151,13 @@ isl_gen8_choose_image_alignment_el(const struct isl_device *dev,
*/
const uint32_t valign = 4;
- bool needs_halign16 = false;
+ /* XXX(chadv): I believe the hardware requires each image to be
+ * cache-aligned. If that's true, then defaulting to halign=4 is wrong for
+ * many formats. Depending on the format's block size, we may need to
+ * increase halign to 8.
+ */
+ uint32_t halign = 4;
+
if (!(info->usage & ISL_SURF_USAGE_DISABLE_AUX_BIT)) {
/* From the Broadwell PRM, Volume 2d "Command Reference: Structures",
* RENDER_SURFACE_STATE Surface Horizontal Alignment, p326:
@@ -163,15 +169,22 @@ isl_gen8_choose_image_alignment_el(const struct isl_device *dev,
* or CCS_E. Depth buffers, including those that own an auxiliary HiZ
* surface, are handled above and do not require HALIGN_16.
*/
- needs_halign16 = true;
+ assert(halign <= 16);
+ halign = 16;
}
- /* XXX(chadv): I believe the hardware requires each image to be
- * cache-aligned. If that's true, then defaulting to halign=4 is wrong for
- * many formats. Depending on the format's block size, we may need to
- * increase halign to 8.
- */
- const uint32_t halign = needs_halign16 ? 16 : 4;
+ if (ISL_DEV_GEN(dev) >= 11 && isl_tiling_is_any_y(tiling) &&
+ fmtl->bpb == 32 && info->samples == 1) {
+ /* GEN_BUG_1406667188: Pixel Corruption in subspan combining (8x4
+ * combining) scenarios if halign=4.
+ *
+ * See RENDER_SURFACE_STATE in Ice Lake h/w spec:
+ *
+ * "For surface format = 32 bpp, num_multisamples = 1 , MIpcount > 0
+ * and surface walk = TiledY, HALIGN must be programmed to 8"
+ */
+ halign = MAX(halign, 8);
+ }
*image_align_el = isl_extent3d(halign, valign, 1);
}
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