Mesa (master): iris: Hack up a SKL/Gen9LP PS push constant fifo depth workaround

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Module: Mesa
Branch: master
Commit: 4f857423b3c095516e553b976b41969c2b9721fa
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=4f857423b3c095516e553b976b41969c2b9721fa

Author: Kenneth Graunke <kenneth at whitecape.org>
Date:   Sat Oct  5 15:02:28 2019 -0400

iris: Hack up a SKL/Gen9LP PS push constant fifo depth workaround

This is a port of Nanley's 904c2a617d86944fbdc2c955f327aacd0b3df318
from i965 to iris.

One concern is that iris uses larger batches, and also emits far fewer
commands, so we may come closer to the 500 limit within a batch, and
could need to supplement this with actual counting.  Manhattan 3.0 had
239 3DSTATE_CONSTANT_PS packets in a batch,  Unigine Valley had 155.
So it seems like we're still in the realm of safety.

---

 src/gallium/drivers/iris/iris_state.c | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c
index b66eee791d1..9db8263920b 100644
--- a/src/gallium/drivers/iris/iris_state.c
+++ b/src/gallium/drivers/iris/iris_state.c
@@ -5539,6 +5539,29 @@ iris_upload_render_state(struct iris_context *ice,
 {
    bool use_predicate = ice->state.predicate == IRIS_PREDICATE_STATE_USE_BIT;
 
+   UNUSED const struct gen_device_info *devinfo = &batch->screen->devinfo;
+
+   /* The Skylake PRM's Workarounds section (#878) says:
+    *
+    *   "Push constant buffer corruption possible. WA: Insert 2 zero-length
+    *    PushConst_PS before every intended PushConst_PS update, issue a
+    *    NULLPRIM after each of the zero len PC update to make sure CS commits
+    *    them."
+    *
+    * This workaround is attempting to solve a pixel shader push constant
+    * synchronization issue.
+    *
+    * An unpublished WA suggests re-emitting 3DSTATE_PUSH_CONSTANT_ALLOC_PS
+    * for every 500 or so 3DSTATE_CONSTANT_PS packets.  Since our counting
+    * methods may not be reliable due to context-switching and pre-emption,
+    * we instead choose to approximate this behavior by re-emitting the
+    * packet on the first regular draw of the batch.
+    */
+   if (GEN_GEN == 9 && !batch->contains_draw &&
+       (devinfo->is_skylake || gen_device_info_is_9lp(devinfo))) {
+      iris_alloc_push_constants(batch);
+   }
+
    /* Always pin the binder.  If we're emitting new binding table pointers,
     * we need it.  If not, we're probably inheriting old tables via the
     * context, and need it anyway.  Since true zero-bindings cases are