Mesa (master): 61 new commits

Fri Oct 11 19:31:19 UTC 2019

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=44754279ace72bc36b016f9ca519141ea4cad038
Author: Kenneth Graunke <kenneth at whitecape.org>
Date:   Fri May 3 16:39:18 2019 -0700

    intel/fs/gen12: Use TCS 8_PATCH mode.
    
    Reviewed-by: Francisco Jerez <currojerez at riseup.net>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=c92fb60007f9c73a4c174f5f4cbce57fbc5118f4
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Mon Jun 11 23:21:57 2018 -0700

    intel/fs/gen12: Implement gl_FrontFacing on gen12+.
    
    The bit moved on gen12 in order to prepare for dual-SIMD8 dispatch.
    This implementation isn't an entirely complete as it only works on SIMD8
    and SIMD16 and not dual-SIMD8.
    
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=ceb123befa7a4f79727fc4626833396d2951f37b
Author: Francisco Jerez <currojerez at riseup.net>
Date:   Fri Sep 27 19:13:11 2019 -0700

    intel/fs/gen11+: Fix CS_OPCODE_CS_TERMINATE codegen.
    
    Apparently the ts_request_type and ts_resource_select thread spawner
    message descriptor bits were removed from the hardware at least since
    ICL.  Drop them in order to avoid assertion failures on Gen12+
    platforms which don't have any encoding for this.  On Gen9+ these are
    probably just ignored by the hardware, so this is unlikely to have had
    any functional implications prior to Gen12.
    
    v2: Mark TS message fields as non-existing in brw_inst.h on ICL. (Caio)
    
    Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=a5efb0eae85106bd89537ed755501a59a9cbbc92
Author: Francisco Jerez <currojerez at riseup.net>
Date:   Tue Sep 3 17:31:37 2019 -0700

    intel/fs/gen12: Fix barrier codegen.
    
    The WAIT instruction has been removed, but SYNC.bar can be used
    instead to wait for a notification on n0.0.
    
    Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=6b52f813958648d7ba7ae469cac0c0a53ef1987c
Author: Francisco Jerez <currojerez at riseup.net>
Date:   Tue Sep 3 17:29:11 2019 -0700

    intel/eu: Don't set notify descriptor field of gateway barrier message.
    
    Apparently this field was removed on SKL, and according to the
    hardware docs for previous platforms "This field is only valid for a
    ForwardMsg message. It is ignored for other messages. The BarrierMsg
    message always increments the N0 notification counter".
    
    Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=b0e69d115ef1b2eb69695d4052538c8cad84a0b8
Author: Francisco Jerez <currojerez at riseup.net>
Date:   Thu Aug 22 16:16:26 2019 -0700

    intel/ir/gen12: Update assert in brw_stage_has_packed_dispatch().
    
    Confirmed no regressions after a full Piglit run on TGL with the
    brw_fs_test_dispatch_packing() test enabled.
    
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=ca7b6fd3922cd6eb898e9fb2bac90b9933d3a0af
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Tue Apr 17 17:12:05 2018 -0700

    intel/eu/validate/gen12: Don't blow up on indirect src0.
    
    They look like a NULL source if you don't look at the address mode.
    
    Reviewed-by: Francisco Jerez <currojerez at riseup.net>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=ab5aa016890c5e7a5dbac2544fd8196fa5a995ed
Author: Francisco Jerez <currojerez at riseup.net>
Date:   Tue Feb 5 21:54:38 2019 -0800

    intel/eu/validate/gen12: Validation fixes for SEND instruction.
    
    The following fix-up by Jordan Justen is squashed in:
    
     intel/eu/validate: gen12 send instruction doesn't have a dst type field
    
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=a81f9b5e3e74f102e3178122a581f6fe23d42fec
Author: Francisco Jerez <currojerez at riseup.net>
Date:   Tue Feb 5 21:54:54 2019 -0800

    intel/eu/validate/gen12: Fix validation of SYNC instruction.
    
    src0 will typically be null for this instruction.
    
    Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=45768e6b3c51aebf052f47dd1c2aca5f17b77ed9
Author: Francisco Jerez <currojerez at riseup.net>
Date:   Fri Dec 7 14:09:25 2018 -0800

    intel/eu/validate/gen12: Implement integer multiply restrictions in EU validator.
    
    Due to hardware bug filed as HSDES#1604601757.
    
    Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=f9ec4ac5a146b4ffbeca078179297f847035ef7f
Author: Jordan Justen <jordan.l.justen at intel.com>
Date:   Tue Dec 12 19:01:44 2017 -0800

    intel/ir: Lower fpow on Gen12.
    
    Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
    Reviewed-by: Francisco Jerez <currojerez at riseup.net>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=cb6db5bfb3a3499f4adcfd78393ee34a90c2d376
Author: Francisco Jerez <currojerez at riseup.net>
Date:   Fri Dec 7 14:13:53 2018 -0800

    intel/fs/gen12: Don't support source mods for 32x16 integer multiply.
    
    Due to hardware bug filed as HSDES#1604601757.
    
    v2: Only return if result of fs_inst::can_do_source_mods() is known to
        be false for the case new orthogonal restrictions are implemented
        below in the future. (Caio)
    
    Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=de5d106ccfdc2835d2f9bdd50f379095cd9936ca
Author: Francisco Jerez <currojerez at riseup.net>
Date:   Tue Aug 27 22:02:49 2019 -0700

    intel/disasm: Disassemble register file of split SEND sources.
    
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=c03869323b2d3da648385690b277571be8277886
Author: Francisco Jerez <currojerez at riseup.net>
Date:   Tue Aug 27 22:02:19 2019 -0700

    intel/disasm: Don't disassemble saturate control on SEND instructions.
    
    The field is gone on Gen12+ and it was illegal on previous
    generations.
    
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=f15e0b3439dc005933c560e1f5be66dba629ffdc
Author: Francisco Jerez <currojerez at riseup.net>
Date:   Tue Aug 27 21:52:51 2019 -0700

    intel/disasm/gen12: Disassemble Gen12 SEND instructions.
    
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=fd7e21dd909c218dc161d379b693f9487eafb48f
Author: Francisco Jerez <currojerez at riseup.net>
Date:   Fri Apr 26 17:08:25 2019 -0700

    intel/disasm/gen12: Disassemble Gen12 SYNC instruction.
    
    Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=606d823b42e26a0a6ca66747eeabe1ff56d9b95b
Author: Francisco Jerez <currojerez at riseup.net>
Date:   Fri Nov 9 14:13:37 2018 -0800

    intel/disasm/gen12: Disassemble three-source instruction source and destination regions.
    
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=8263d300c288a4284f19ff60448a1e6c5d1f6253
Author: Francisco Jerez <currojerez at riseup.net>
Date:   Fri Nov 9 14:13:38 2018 -0800

    intel/disasm/gen12: Fix disassembly of some common instruction controls.
    
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=83612c0127130037fac684ed13581abb06af1030
Author: Francisco Jerez <currojerez at riseup.net>
Date:   Fri Nov 9 14:13:38 2018 -0800

    intel/disasm/gen12: Disassemble software scoreboard information.
    
    Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=396f6b27a759246221dd641b14ecc2f0bb7839a7
Author: Francisco Jerez <currojerez at riseup.net>
Date:   Wed Oct 9 18:47:29 2019 -0700

    intel/fs/gen12: Demodernize software scoreboard lowering pass.
    
    Kept as a separate commit in order to avoid distracting reviewers of
    the software scoreboard pass with memory management boilerplate.
    
    Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=265c7c897173e34920ca269aa1fae7285ec1c5a5
Author: Francisco Jerez <currojerez at riseup.net>
Date:   Fri Nov 9 14:13:37 2018 -0800

    intel/fs/gen12: Introduce software scoreboard lowering pass.
    
    Gen12+ hardware lacks the register scoreboard logic that used to
    guarantee data coherency between register reads and writes in previous
    generations.  This lowering pass runs after register allocation in
    order to make up for it.
    
    It works by performing global dataflow analysis in order to determine
    the set of potential dependencies of every instruction in the shader,
    and then inserts any required SWSB annotations and additional SYNC
    instructions in order to guarantee data coherency.
    
    v2: Drop unnecessary _safe list iteration (Caio).
    
    v3: Temporarily workaround potential WaR hazard between FPU
        instruction and subsequent out-of-order write, pending
        clarification from the hardware team.  Drop redundant tracking of
        implicit access of acc0-1, since the hardware guarantees coherency
        of these (but not the other accumulators...).
    
    Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=e0b8d7953ea405cfbed0b2a1b0a526f8c65bf596
Author: Francisco Jerez <currojerez at riseup.net>
Date:   Fri Nov 9 14:13:37 2018 -0800

    intel/fs/gen12: Add scheduling information to the IR.
    
    Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=15e3a0d9d264beccb914432ca749d7c0b8a5d43c
Author: Francisco Jerez <currojerez at riseup.net>
Date:   Thu Sep 26 23:38:24 2019 -0700

    intel/eu/gen12: Set SWSB annotations in hand-crafted assembly.
    
    Reviewers are encouraged to audit the code generation pass
    independently for the case I missed some potential data hazard or new
    code has been added in the meantime.
    
    v2: Add SYNC instruction to cr0 workaround in brw_float_controls_mode().
    
    v3: Drop likely redundant (and potentially harmful) RegDist SWSB
        annotation from ce0 read in brw_find_live_channel() (Caio).
    
    Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=d3f3bdcd185312885351a9812be03086012e85dd
Author: Francisco Jerez <currojerez at riseup.net>
Date:   Fri Nov 9 14:13:36 2018 -0800

    intel/eu/gen12: Add tracking of default SWSB state to the current brw_codegen instruction.
    
    Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=6154cdf924f4d0d3a6fb0cef38bc62eb4494c69c
Author: Francisco Jerez <currojerez at riseup.net>
Date:   Fri Nov 9 14:13:36 2018 -0800

    intel/eu/gen12: Add auxiliary type to represent SWSB information during codegen.
    
    v2: Introduce extra tgl_swsb_sbid() constructor (Caio).
    
    Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=c22db5e1885ffbc4eb658bb27d3638749d425b03
Author: Francisco Jerez <currojerez at riseup.net>
Date:   Tue Sep 3 17:51:17 2019 -0700

    intel/fs/gen12: Add codegen support for the SYNC instruction.
    
    Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=0e57dbc55cd7f42a2298dbaa4e18fe97a85fd0d2
Author: Francisco Jerez <currojerez at riseup.net>
Date:   Tue Feb 5 20:53:06 2019 -0800

    intel/ir/gen12: Add SYNC hardware instruction.
    
    Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=7499e10383bb4182b1bf3edb90e1915fdf0c6d33
Author: Francisco Jerez <currojerez at riseup.net>
Date:   Thu Sep 26 23:36:58 2019 -0700

    intel/eu/gen12: Don't set thread control, it's gone.
    
    An effect similar to the one formerly provided by setting thread
    control to "switch" can be achieved now by setting a RegDist of 1 on
    the SWSB field.
    
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=a66ea33991a8542144997a55649878cde07e3e3e
Author: Francisco Jerez <currojerez at riseup.net>
Date:   Fri Nov 9 14:13:36 2018 -0800

    intel/eu/gen12: Don't set DD control, it's gone.
    
    A future lowering pass will simulate the same behavior originally
    provided by NoDDChk/NoDDClr at the IR level by using appropriate SWSB
    annotations.
    
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=8a5fad0d926a18ef998dc866dff9e466778c899c
Author: Francisco Jerez <currojerez at riseup.net>
Date:   Sun Aug 25 18:12:35 2019 -0700

    intel/eu/gen12: Use SEND instruction for split sends.
    
    The new SEND instruction behaves like the former SENDS instruction.
    The original single-payload SEND instruction is gone.
    
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=6634ede7aac30ac8d21b9acc9a67010927ec93eb
Author: Francisco Jerez <currojerez at riseup.net>
Date:   Tue Sep 3 12:18:38 2019 -0700

    intel/eu/gen12: Codegen SEND descriptor regions correctly.
    
    The SEND instruction is now four-source.  The descriptor is no longer
    part of source 1, so avoid touching it to avoid corruption while
    initializing the descriptor.
    
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=2c4c9aba309ec40b00bc681bf75e20c9ae2f7cb0
Author: Francisco Jerez <currojerez at riseup.net>
Date:   Sun Aug 25 18:13:42 2019 -0700

    intel/eu/gen12: Codegen pathological SEND source and destination regions.
    
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=bafc9515db0b07521043f1255eeed01bd2eb223b
Author: Francisco Jerez <currojerez at riseup.net>
Date:   Fri Nov 9 14:13:35 2018 -0800

    intel/eu/gen12: Codegen control flow instructions correctly.
    
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=6e1daba3b46db3a874819dc41511a13bcf71e9d9
Author: Francisco Jerez <currojerez at riseup.net>
Date:   Fri Nov 9 14:13:35 2018 -0800

    intel/eu/gen12: Codegen three-source instruction source and destination regions.
    
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=9fdb67aa0979418069f241f20584c9913e65f302
Author: Francisco Jerez <currojerez at riseup.net>
Date:   Sun Aug 25 17:52:54 2019 -0700

    intel/eu/gen12: Fix codegen of immediate source regions.
    
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=6cb764ae9cd0e6b533699f7e55cec401c10907b7
Author: Francisco Jerez <currojerez at riseup.net>
Date:   Fri Nov 9 14:13:35 2018 -0800

    intel/eu/gen12: Add Gen12 opcode descriptions to the table.
    
    Quite a lot of churn because the encoding of most hardware opcodes has
    changed unfortunately.
    
    v2: Split dot-product description fixes to separate patch (Caio).
    
    Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=31182e7aa95be5c999bda51b8a2575bed59fc621
Author: Francisco Jerez <currojerez at riseup.net>
Date:   Fri Sep 27 15:52:31 2019 -0700

    intel/eu/gen11+: Mark dot product opcodes as unsupported on opcode_descs table.
    
    These instructions have been removed from the hardware.
    
    Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=c742be143731cf34c97a67e795e488844fe479e9
Author: Francisco Jerez <currojerez at riseup.net>
Date:   Fri Nov 9 14:13:35 2018 -0800

    intel/eu/gen12: Implement datatype binary encoding.
    
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=a12533f2ce2e5a4aeae0f1fc8d759de73bdb6e2d
Author: Sagar Ghuge <sagar.ghuge at intel.com>
Date:   Thu Nov 15 16:19:39 2018 -0800

    intel/eu/gen12: Implement immediate 64 bit constant encoding.
    
    On Gen12, 64 bit immediate constants are loaded in reverse order. Lower
    32 bit gets loaded from bit 96-127 and higher 32 bits from 64-95 in
    instruction encoding.
    
    Signed-off-by: Sagar Ghuge <sagar.ghuge at intel.com>
    Co-authored-by: Matt Turner <mattst88 at gmail.com>
    Reviewed-by: Francisco Jerez <currojerez at riseup.net>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
    Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=5291283af0fbcbc96888f63f78bd6480fc70fcc1
Author: Francisco Jerez <currojerez at riseup.net>
Date:   Fri Nov 9 14:13:34 2018 -0800

    intel/eu/gen12: Implement compact instruction binary encoding.
    
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
    Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=77d09d0d50dbd5b208990cd93ee2c841fca1977a
Author: Francisco Jerez <currojerez at riseup.net>
Date:   Fri Nov 9 14:13:34 2018 -0800

    intel/eu/gen12: Implement indirect region binary encoding.
    
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
    Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=81400470bea0f91584a3473bf2a14de89e6e138e
Author: Francisco Jerez <currojerez at riseup.net>
Date:   Sat Aug 24 15:28:08 2019 -0700

    intel/eu/gen12: Implement SEND instruction binary encoding.
    
    v2: Fix off-by-one upper GET_BITS() bound, combine 25-29 and 30-31
        descriptor fields (Ken).  Shorten name of GEN12_MD() macro, drop
        some removed TS message descriptor fields (Jordan).
    
    Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=d24b8af23daffed650cca88ca4e29add4b598d14
Author: Francisco Jerez <currojerez at riseup.net>
Date:   Thu Aug 22 18:14:12 2019 -0700

    intel/eu/gen12: Implement control flow instruction binary encoding.
    
    Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=956c156dc494b0ba39287e241c75682334aa8fef
Author: Francisco Jerez <currojerez at riseup.net>
Date:   Sat Aug 24 18:12:43 2019 -0700

    intel/eu/gen12: Implement three-source instruction binary encoding.
    
    Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=fa482817951e9f3fbd577f42110a0d7fe74f3277
Author: Francisco Jerez <currojerez at riseup.net>
Date:   Fri Aug 23 22:49:08 2019 -0700

    intel/eu/gen12: Implement basic instruction binary encoding.
    
    Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=143176163d39720fa040b441be6290286590e5cf
Author: Francisco Jerez <currojerez at riseup.net>
Date:   Fri Nov 9 14:13:35 2018 -0800

    intel/eu/gen12: Add sanity-check asserts to brw_inst_bits() and brw_inst_set_bits().
    
    These caught a few bugs during the development of this series.
    
    Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
    Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=7e5a8638d3a2a3b0fdd71be196ce241714827dd6
Author: Francisco Jerez <currojerez at riseup.net>
Date:   Thu Aug 22 17:52:11 2019 -0700

    intel/eu/gen12: Extend brw_inst.h macros for Gen12 support.
    
    The encoding of almost every instruction field has changed in Gen12,
    so this involves adding a Gen12+ bitfield spec to every brw_inst
    macro.  In addition some new macros are required to handle certain
    discontiguous and variable-length fields.
    
    This commit doesn't actually include the Gen12 updated bitfield specs,
    only the macros are extended here for reviewability.
    
    Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
    
    v2: Rename FDC() to FFDC() and FDC1() to FDC() for consistency with
        the existing F() and FF() macros.

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=6965a02e09de2d31e5fa951ffa2ae401b2197fb1
Author: Francisco Jerez <currojerez at riseup.net>
Date:   Fri Sep 27 14:50:00 2019 -0700

    intel/ir: Represent physical edge of unconditional CONTINUE instruction.
    
    This edge doesn't exist in the original scalar program, but it
    represents a potential control flow path the EU will take in cases
    where control flow isn't uniform across channels of the same SIMD
    thread.
    
    Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
    Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=eeaad2992cc45c22f5e188d0a814db795112964d
Author: Francisco Jerez <currojerez at riseup.net>
Date:   Fri Sep 27 14:49:42 2019 -0700

    intel/ir: Represent physical edge of ELSE instruction.
    
    This edge doesn't exist in the original scalar program, but it
    represents a potential control flow path the EU will take in cases
    where the condition isn't uniform across channels of the same SIMD
    thread.
    
    Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
    Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=152754665abb937a49e451331c88266ef5c3cdf1
Author: Francisco Jerez <currojerez at riseup.net>
Date:   Mon Aug 5 18:21:05 2019 -0700

    intel/ir: Represent logical edge of BREAK instruction.
    
    Currently only the physical back-edge is represented, which
    incidentally also leads to the exit block of the loop, but we need the
    direct logical edge in addition for our logical CFG representation to
    be complete.
    
    Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
    Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=c344c92b31454115261d6f235d00e4e14ed0ce3c
Author: Francisco Jerez <currojerez at riseup.net>
Date:   Fri Sep 27 14:49:14 2019 -0700

    intel/ir: Add helper function to push block onto CFG analysis stack.
    
    Requested-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
    Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=d6a9731d8f94c4ecaea69bed6034f8a605838b6d
Author: Francisco Jerez <currojerez at riseup.net>
Date:   Mon Aug 5 17:36:40 2019 -0700

    intel/ir: Represent physical and logical subsets of the CFG.
    
    This represents two control flow graphs in the same cfg_t data
    structure: The physical CFG that will include all possible control
    flow paths the EU can physically take, and the logical CFG restricted
    to the control flow paths that exist in the original scalar program.
    The latter is a subset of the former because in case of divergence the
    SIMD vectorized program will take control flow paths that aren't part
    of the original scalar program.
    
    The bblock_link constructor and bblock_t::add_successor() now take a
    "kind" parameter that specifies whether the edge is purely physical or
    whether it's part of both the logical and physical CFGs (a logical
    edge is of course always guaranteed to be in the physical CFG as
    well).  bblock_t::is_predecessor_of() and ::is_successor_of() also
    take a kind parameter specifying which CFG is being queried.  The '~>'
    notation will be used now in order to represent purely physical edges
    in IR dumps.
    
    This commit doesn't actually add nor remove any edges from the CFG
    (the only edges marked as purely physical here are the two WHILE loop
    ones that already existed).  Optimization passes should continue using
    the same (incomplete) physical CFG they were using before until
    they're fixed to do something smarter in a later commit, so this
    shouldn't lead to any functional changes.
    
    v2: Remove tabs from lines changed in this file (Caio).
    
    Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
    Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=1b570456caecac5371dec9383a50f4f9877d3a61
Author: Francisco Jerez <currojerez at riseup.net>
Date:   Tue Jan 23 19:38:45 2018 -0800

    intel/ir: Drop hard-coded correspondence between IR and HW opcodes.
    
    Having the IR opcodes locked to their hardware representation is risky
    because it causes opcodes as different as BRC and IFF to compare equal
    at the IR level (luckily the back-end only ever uses one opcode from
    each group, right now), and it prevents us from supporting
    instructions that change their hardware representation across
    generations, which will become a problem on Gen12+ platforms.
    
    Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
    Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=057902dcf8d287f0b110b03f67ae33d338a7497c
Author: Francisco Jerez <currojerez at riseup.net>
Date:   Tue Jan 23 19:23:20 2018 -0800

    intel/eu: Encode and decode native instruction opcodes from/to IR opcodes.
    
    Change brw_inst_set_opcode() and brw_inst_opcode() to call
    brw_opcode_encode/decode() transparently in order to translate between
    hardware and IR opcodes, and update the EU compaction code in order to
    do the same as needed, so we can eventually drop the one-to-one
    correspondence between hardware and IR opcodes.
    
    Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
    Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=25dd67099df301f09ce40b8f9c5a3bbc857e367c
Author: Francisco Jerez <currojerez at riseup.net>
Date:   Mon Jun 11 12:54:17 2018 -0700

    intel/eu: Rework opcode description tables to allow efficient look-up by either HW or IR opcode.
    
    This rewrites the current opcode description tables as a more compact
    flat data structure.  The purpose is to allow efficient constant-time
    look-up by either HW or IR opcode, which will allow us to drop the
    hard-coded correspondence between HW and IR opcodes -- See the next
    commits for the rationale.
    
    brw_eu.c is now built as C++ source so we can take advantage of
    pointers to member in order to make the look-up function work
    regardless of the opcode_desc member used as look-up key.
    
    v2: Optimize devinfo struct comparison (Caio)
    
    Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
    Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=51dc40cefb0b04726668bb3f3ee0e51cdaf30d72
Author: Francisco Jerez <currojerez at riseup.net>
Date:   Thu Jun 7 15:32:15 2018 -0700

    intel/eu: Fix up various type conversions in brw_eu.c that are illegal C++.
    
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
    Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
    Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=35bcd08d612a992a067e54b3dbaffc330d3009ba
Author: Francisco Jerez <currojerez at riseup.net>
Date:   Tue Feb 5 23:22:06 2019 -0800

    intel/eu: Split brw_inst ex_desc accessors for SEND(C) vs. SENDS(C).
    
    The brw_inst opcode accessors are going away in one of the following
    commits.  We could potentially replace them with the new helpers that
    do opcode remapping, but that would lead to a circular dependency
    between brw_inst.h and brw_eu.h.  This way we also avoid ordering
    issues that can cause the semantics of the ex_desc accessors to change
    depending on whether the ex_desc field is set after or before the
    opcode instruction field.
    
    Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
    Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=b2ae65c7d93bb95dc8dbd14b61e58d60cfcee932
Author: Francisco Jerez <currojerez at riseup.net>
Date:   Fri Nov 9 14:13:37 2018 -0800

    intel/fs: Fix constness of implied_mrf_writes() argument.
    
    Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
    Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=6f275a863dd5a4babc9ee9de792c401c0eb7cb0d
Author: Francisco Jerez <currojerez at riseup.net>
Date:   Mon Aug 26 00:12:26 2019 -0700

    intel/fs: Define is_send() convenience IR helper.
    
    Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
    Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=f326d9d218d33a45f79d92bcb2bb04da9061a300
Author: Francisco Jerez <currojerez at riseup.net>
Date:   Fri Nov 9 14:13:37 2018 -0800

    intel/fs: Define is_payload() method of the IR instruction class.
    
    This is required because SEND message payload sources are fetched
    asynchronously by the hardware, which can lead to WaR data corruption
    on Gen12+ platforms if not handled specially by the compiler to
    guarantee proper synchronization.
    
    Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
    Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=a42581fa8f28f282c9faaeb948c3bb192b4a979e
Author: Francisco Jerez <currojerez at riseup.net>
Date:   Fri Apr 26 17:11:42 2019 -0700

    intel/fs: Teach fs_inst::is_send_from_grf() about some missing send-like instructions.
    
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
    Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
    Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>