Mesa (master): intel/isl: Select Y-tiling for stencil on gen12
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Thu Oct 17 21:52:17 UTC 2019
Module: Mesa
Branch: master
Commit: d9565160b289b8ebf3d953e57e156382bc62ecc3
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d9565160b289b8ebf3d953e57e156382bc62ecc3
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon Jan 8 16:28:46 2018 -0800
intel/isl: Select Y-tiling for stencil on gen12
Rework:
* Disallow linear 1D stencil buffers (Nanley)
* Force Y for gen12 stencil rather than ~W (Nanley)
Co-authored-by: Nanley Chery <nanley.g.chery at intel.com>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
Reviewed-by: Nanley Chery <nanley.g.chery at intel.com>
---
src/intel/isl/isl_gen7.c | 11 +++++++----
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/src/intel/isl/isl_gen7.c b/src/intel/isl/isl_gen7.c
index a9db21fba52..e1feae9b375 100644
--- a/src/intel/isl/isl_gen7.c
+++ b/src/intel/isl/isl_gen7.c
@@ -213,11 +213,14 @@ isl_gen6_filter_tiling(const struct isl_device *dev,
*flags &= ISL_TILING_ANY_Y_MASK;
}
- /* Separate stencil requires W tiling, and W tiling requires separate
- * stencil.
- */
if (isl_surf_usage_is_stencil(info->usage)) {
- *flags &= ISL_TILING_W_BIT;
+ if (ISL_DEV_GEN(dev) >= 12) {
+ /* Stencil requires Y. */
+ *flags &= ISL_TILING_ANY_Y_MASK;
+ } else {
+ /* Stencil requires W. */
+ *flags &= ISL_TILING_W_BIT;
+ }
} else {
*flags &= ~ISL_TILING_W_BIT;
}
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