Mesa (master): freedreno/ir3: rename mul.s/mul.u

[GitLab Mirror]

Module: Mesa
Branch: master
Commit: 6ad442acae6c23397e3fd6dcd2fb8972f271e41f
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=6ad442acae6c23397e3fd6dcd2fb8972f271e41f

Author: Rob Clark <robdclark at chromium.org>
Date:   Wed Sep 25 10:21:24 2019 -0700

freedreno/ir3: rename mul.s/mul.u

to mul.s24/mul.u24, to better reflect that these are 24b multiply.

Signed-off-by: Rob Clark <robdclark at chromium.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg at google.com>
Reviewed-by: Eduardo Lima Mitev <elima at igalia.com>

---

 src/freedreno/ir3/disasm-a3xx.c      |  4 ++--
 src/freedreno/ir3/instr-a3xx.h       |  4 ++--
 src/freedreno/ir3/ir3.h              | 12 ++++++------
 src/freedreno/ir3/ir3_a4xx.c         |  2 +-
 src/freedreno/ir3/ir3_compiler_nir.c |  2 +-
 5 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/src/freedreno/ir3/disasm-a3xx.c b/src/freedreno/ir3/disasm-a3xx.c
index a5e1afc8de6..093a38fa9b5 100644
--- a/src/freedreno/ir3/disasm-a3xx.c
+++ b/src/freedreno/ir3/disasm-a3xx.c
@@ -914,8 +914,8 @@ static const struct opc_info {
 	OPC(2, OPC_XOR_B,        xor.b),
 	OPC(2, OPC_CMPV_U,       cmpv.u),
 	OPC(2, OPC_CMPV_S,       cmpv.s),
-	OPC(2, OPC_MUL_U,        mul.u),
-	OPC(2, OPC_MUL_S,        mul.s),
+	OPC(2, OPC_MUL_U24,      mul.u24),
+	OPC(2, OPC_MUL_S24,      mul.s24),
 	OPC(2, OPC_MULL_U,       mull.u),
 	OPC(2, OPC_BFREV_B,      bfrev.b),
 	OPC(2, OPC_CLZ_S,        clz.s),
diff --git a/src/freedreno/ir3/instr-a3xx.h b/src/freedreno/ir3/instr-a3xx.h
index 3887736444d..29f2bd781bc 100644
--- a/src/freedreno/ir3/instr-a3xx.h
+++ b/src/freedreno/ir3/instr-a3xx.h
@@ -90,8 +90,8 @@ typedef enum {
 	OPC_CMPV_U          = _OPC(2, 33),
 	OPC_CMPV_S          = _OPC(2, 34),
 	/* 35-47 - invalid */
-	OPC_MUL_U           = _OPC(2, 48),
-	OPC_MUL_S           = _OPC(2, 49),
+	OPC_MUL_U24         = _OPC(2, 48), /* 24b mul into 32b result */
+	OPC_MUL_S24         = _OPC(2, 49), /* 24b mul into 32b result with sign extension */
 	OPC_MULL_U          = _OPC(2, 50),
 	OPC_BFREV_B         = _OPC(2, 51),
 	OPC_CLZ_S           = _OPC(2, 52),
diff --git a/src/freedreno/ir3/ir3.h b/src/freedreno/ir3/ir3.h
index 8b7bdc618b2..4fc65a90c92 100644
--- a/src/freedreno/ir3/ir3.h
+++ b/src/freedreno/ir3/ir3.h
@@ -860,8 +860,8 @@ static inline bool ir3_cat2_int(opc_t opc)
 	case OPC_MAX_S:
 	case OPC_CMPV_U:
 	case OPC_CMPV_S:
-	case OPC_MUL_U:
-	case OPC_MUL_S:
+	case OPC_MUL_U24:
+	case OPC_MUL_S24:
 	case OPC_MULL_U:
 	case OPC_CLZ_S:
 	case OPC_ABSNEG_S:
@@ -953,8 +953,8 @@ static inline unsigned ir3_cat2_absneg(opc_t opc)
 	case OPC_MAX_S:
 	case OPC_CMPV_U:
 	case OPC_CMPV_S:
-	case OPC_MUL_U:
-	case OPC_MUL_S:
+	case OPC_MUL_U24:
+	case OPC_MUL_S24:
 	case OPC_MULL_U:
 	case OPC_CLZ_S:
 		return 0;
@@ -1335,8 +1335,8 @@ INSTR1(NOT_B)
 INSTR2(XOR_B)
 INSTR2(CMPV_U)
 INSTR2(CMPV_S)
-INSTR2(MUL_U)
-INSTR2(MUL_S)
+INSTR2(MUL_U24)
+INSTR2(MUL_S24)
 INSTR2(MULL_U)
 INSTR1(BFREV_B)
 INSTR1(CLZ_S)
diff --git a/src/freedreno/ir3/ir3_a4xx.c b/src/freedreno/ir3/ir3_a4xx.c
index e1d188652b8..dd654bacc7c 100644
--- a/src/freedreno/ir3/ir3_a4xx.c
+++ b/src/freedreno/ir3/ir3_a4xx.c
@@ -225,7 +225,7 @@ get_image_offset(struct ir3_context *ctx, const nir_variable *var,
 			(1 << var->data.driver_location));
 
 	/* offset = coords.x * bytes_per_pixel: */
-	offset = ir3_MUL_S(b, coords[0], 0, create_uniform(b, cb + 0), 0);
+	offset = ir3_MUL_S24(b, coords[0], 0, create_uniform(b, cb + 0), 0);
 	if (ncoords > 1) {
 		/* offset += coords.y * y_pitch: */
 		offset = ir3_MAD_S24(b, create_uniform(b, cb + 1), 0,
diff --git a/src/freedreno/ir3/ir3_compiler_nir.c b/src/freedreno/ir3/ir3_compiler_nir.c
index 0e891041e1b..c1501d81b90 100644
--- a/src/freedreno/ir3/ir3_compiler_nir.c
+++ b/src/freedreno/ir3/ir3_compiler_nir.c
@@ -2457,7 +2457,7 @@ emit_stream_out(struct ir3_context *ctx)
 		base = create_uniform(ctx->block, regid(const_state->offsets.tfbo, i));
 
 		/* 24-bit should be enough: */
-		off = ir3_MUL_U(ctx->block, vtxcnt, 0,
+		off = ir3_MUL_U24(ctx->block, vtxcnt, 0,
 				create_immed(ctx->block, stride * 4), 0);
 
 		bases[i] = ir3_ADD_S(ctx->block, off, 0, base, 0);