Mesa (master): radv: fix updating bound fast ds clear values with different aspects

[GitLab Mirror]

Module: Mesa
Branch: master
Commit: a13320370ef4b668ace96ecba7eb0f8591af6f79
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=a13320370ef4b668ace96ecba7eb0f8591af6f79

Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date:   Mon Oct 21 22:17:43 2019 +0200

radv: fix updating bound fast ds clear values with different aspects

On GFX9, the driver is able to do an optimized fast depth/stencil
clear with only one aspect (ie. clear the stencil part of a
depth/stencil image). When this happens, the driver should only
update the clear values of the given aspect.

Note that it's currently only supported on GFX9 but I have some
local patches that extend this optimized path for other gens.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1967
Cc: 19.2 <mesa-stable at lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>

---

 src/amd/vulkan/radv_cmd_buffer.c | 16 +++++++++++++---
 1 file changed, 13 insertions(+), 3 deletions(-)

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 01a0787dcf5..6a9002eaa44 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -1553,9 +1553,19 @@ radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
 	if (cmd_buffer->state.attachments[att_idx].iview->image != image)
 		return;
 
-	radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
-	radeon_emit(cs, ds_clear_value.stencil);
-	radeon_emit(cs, fui(ds_clear_value.depth));
+	if (aspects == (VK_IMAGE_ASPECT_DEPTH_BIT |
+			VK_IMAGE_ASPECT_STENCIL_BIT)) {
+		radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
+		radeon_emit(cs, ds_clear_value.stencil);
+		radeon_emit(cs, fui(ds_clear_value.depth));
+	} else if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT) {
+		radeon_set_context_reg_seq(cs, R_02802C_DB_DEPTH_CLEAR, 1);
+		radeon_emit(cs, fui(ds_clear_value.depth));
+	} else {
+		assert(aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
+		radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 1);
+		radeon_emit(cs, ds_clear_value.stencil);
+	}
 
 	/* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
 	 * only needed when clearing Z to 0.0.