Mesa (master): intel/genxml: add RPSTAT register for core frequency

GitLab Mirror gitlab-mirror at kemper.freedesktop.org
Wed Oct 23 05:43:36 UTC 2019


Module: Mesa
Branch: master
Commit: a2a1873a8289157490876acc4ea2f36886817690
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=a2a1873a8289157490876acc4ea2f36886817690

Author: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Date:   Fri Oct 11 15:53:16 2019 +0300

intel/genxml: add RPSTAT register for core frequency

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli at intel.com>

---

 src/intel/genxml/gen10.xml | 5 +++++
 src/intel/genxml/gen11.xml | 5 +++++
 src/intel/genxml/gen12.xml | 5 +++++
 src/intel/genxml/gen6.xml  | 5 +++++
 src/intel/genxml/gen7.xml  | 5 +++++
 src/intel/genxml/gen75.xml | 5 +++++
 src/intel/genxml/gen8.xml  | 5 +++++
 src/intel/genxml/gen9.xml  | 5 +++++
 8 files changed, 40 insertions(+)

diff --git a/src/intel/genxml/gen10.xml b/src/intel/genxml/gen10.xml
index 498c7073f4a..933d4cbf15e 100644
--- a/src/intel/genxml/gen10.xml
+++ b/src/intel/genxml/gen10.xml
@@ -6833,6 +6833,11 @@
     <field name="MA1 Done SS0" start="26" end="26" type="bool"/>
   </register>
 
+  <register name="RPSTAT0" length="1" num="0xa01c">
+    <field name="Previous GT Frequency" start="0" end="8" type="uint"/>
+    <field name="Current GT Frequency" start="23" end="31" type="uint"/>
+  </register>
+
   <register name="SAMPLER_INSTDONE" length="1" num="0xe160">
     <field name="IME Done" start="0" end="0" type="bool"/>
     <field name="PL0 Done" start="1" end="1" type="bool"/>
diff --git a/src/intel/genxml/gen11.xml b/src/intel/genxml/gen11.xml
index e47c6b2fa51..fbd76ec546a 100644
--- a/src/intel/genxml/gen11.xml
+++ b/src/intel/genxml/gen11.xml
@@ -7046,6 +7046,11 @@
     <field name="MA1 Done SS0" start="26" end="26" type="bool"/>
   </register>
 
+  <register name="RPSTAT0" length="1" num="0xa01c">
+    <field name="Previous GT Frequency" start="0" end="8" type="uint"/>
+    <field name="Current GT Frequency" start="23" end="31" type="uint"/>
+  </register>
+
   <register name="SAMPLER_INSTDONE" length="1" num="0xe160">
     <field name="IME Done" start="0" end="0" type="bool"/>
     <field name="PL0 Done" start="1" end="1" type="bool"/>
diff --git a/src/intel/genxml/gen12.xml b/src/intel/genxml/gen12.xml
index f890df96d51..05d70551aa4 100644
--- a/src/intel/genxml/gen12.xml
+++ b/src/intel/genxml/gen12.xml
@@ -7054,6 +7054,11 @@
     <field name="MA1 Done SS0" start="26" end="26" type="bool"/>
   </register>
 
+  <register name="RPSTAT0" length="1" num="0xa01c">
+    <field name="Previous GT Frequency" start="0" end="8" type="uint"/>
+    <field name="Current GT Frequency" start="23" end="31" type="uint"/>
+  </register>
+
   <register name="SAMPLER_INSTDONE" length="1" num="0xe160">
     <field name="IME Done" start="0" end="0" type="bool"/>
     <field name="PL0 Done" start="1" end="1" type="bool"/>
diff --git a/src/intel/genxml/gen6.xml b/src/intel/genxml/gen6.xml
index d78e2fcc09e..3c52347d370 100644
--- a/src/intel/genxml/gen6.xml
+++ b/src/intel/genxml/gen6.xml
@@ -2890,6 +2890,11 @@
     <field name="Buffer Length (in pages - 1)" start="12" end="20" type="uint"/>
   </register>
 
+  <register name="RPSTAT1" length="1" num="0xa01c">
+    <field name="Previous GT Frequency" start="0" end="6" type="uint"/>
+    <field name="Current GT Frequency" start="7" end="14" type="uint"/>
+  </register>
+
   <register name="VCS_FAULT_REG" length="1" num="0x4194">
     <field name="Valid Bit" start="0" end="0" type="bool"/>
     <field name="Fault Type" start="1" end="2" type="uint">
diff --git a/src/intel/genxml/gen7.xml b/src/intel/genxml/gen7.xml
index efede2b3133..821e2d0230a 100644
--- a/src/intel/genxml/gen7.xml
+++ b/src/intel/genxml/gen7.xml
@@ -3846,6 +3846,11 @@
     <field name="MA1 Done" start="25" end="25" type="bool"/>
   </register>
 
+  <register name="RPSTAT1" length="1" num="0xa01c">
+    <field name="Previous GT Frequency" start="0" end="6" type="uint"/>
+    <field name="Current GT Frequency" start="7" end="14" type="uint"/>
+  </register>
+
   <register name="SAMPLER_INSTDONE" length="1" num="0xe160">
     <field name="VME Done" start="0" end="0" type="bool"/>
     <field name="PL0 Done" start="1" end="1" type="bool"/>
diff --git a/src/intel/genxml/gen75.xml b/src/intel/genxml/gen75.xml
index 1d74da370cd..4cec04b8642 100644
--- a/src/intel/genxml/gen75.xml
+++ b/src/intel/genxml/gen75.xml
@@ -4260,6 +4260,11 @@
     <field name="MA1 Done SS0" start="26" end="26" type="bool"/>
   </register>
 
+  <register name="RPSTAT1" length="1" num="0xa01c">
+    <field name="Previous GT Frequency" start="0" end="6" type="uint"/>
+    <field name="Current GT Frequency" start="7" end="14" type="uint"/>
+  </register>
+
   <register name="SAMPLER_INSTDONE" length="1" num="0xe160">
     <field name="IME Done" start="0" end="0" type="bool"/>
     <field name="PL0 Done" start="1" end="1" type="bool"/>
diff --git a/src/intel/genxml/gen8.xml b/src/intel/genxml/gen8.xml
index 3d6eb821689..916bd63835f 100644
--- a/src/intel/genxml/gen8.xml
+++ b/src/intel/genxml/gen8.xml
@@ -4810,6 +4810,11 @@
     <field name="MA1 Done SS0" start="26" end="26" type="bool"/>
   </register>
 
+  <register name="RPSTAT1" length="1" num="0xa01c">
+    <field name="Previous GT Frequency" start="0" end="6" type="uint"/>
+    <field name="Current GT Frequency" start="7" end="14" type="uint"/>
+  </register>
+
   <register name="SAMPLER_INSTDONE" length="1" num="0xe160">
     <field name="IME Done" start="0" end="0" type="bool"/>
     <field name="PL0 Done" start="1" end="1" type="bool"/>
diff --git a/src/intel/genxml/gen9.xml b/src/intel/genxml/gen9.xml
index 74bf621d91d..95e3558fcef 100644
--- a/src/intel/genxml/gen9.xml
+++ b/src/intel/genxml/gen9.xml
@@ -6674,6 +6674,11 @@
     <field name="MA1 Done SS0" start="26" end="26" type="bool"/>
   </register>
 
+  <register name="RPSTAT0" length="1" num="0xa01c">
+    <field name="Previous GT Frequency" start="0" end="8" type="uint"/>
+    <field name="Current GT Frequency" start="23" end="31" type="uint"/>
+  </register>
+
   <register name="SAMPLER_INSTDONE" length="1" num="0xe160">
     <field name="IME Done" start="0" end="0" type="bool"/>
     <field name="PL0 Done" start="1" end="1" type="bool"/>




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