Mesa (master): iris/gen12: Write GFX_AUX_TABLE base address register
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Mon Oct 28 07:46:34 UTC 2019
Module: Mesa
Branch: master
Commit: 2e6a7ced4dbc70149280fe3c8c453a228c73c524
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2e6a7ced4dbc70149280fe3c8c453a228c73c524
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Fri Apr 27 16:39:30 2018 -0700
iris/gen12: Write GFX_AUX_TABLE base address register
Rework:
* Move last_aux_map_state to iris_batch. (Nanley, Ken)
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
---
src/gallium/drivers/iris/iris_batch.h | 2 ++
src/gallium/drivers/iris/iris_blorp.c | 4 ++++
src/gallium/drivers/iris/iris_context.c | 1 +
src/gallium/drivers/iris/iris_genx_protos.h | 2 ++
src/gallium/drivers/iris/iris_state.c | 33 +++++++++++++++++++++++++++++
5 files changed, 42 insertions(+)
diff --git a/src/gallium/drivers/iris/iris_batch.h b/src/gallium/drivers/iris/iris_batch.h
index 557ba8dbfea..aaa425f5736 100644
--- a/src/gallium/drivers/iris/iris_batch.h
+++ b/src/gallium/drivers/iris/iris_batch.h
@@ -126,6 +126,8 @@ struct iris_batch {
/** Have we emitted any draw calls to this batch? */
bool contains_draw;
+
+ uint32_t last_aux_map_state;
};
void iris_init_batch(struct iris_batch *batch,
diff --git a/src/gallium/drivers/iris/iris_blorp.c b/src/gallium/drivers/iris/iris_blorp.c
index d6b99c59ca7..a1c0dbbcf4e 100644
--- a/src/gallium/drivers/iris/iris_blorp.c
+++ b/src/gallium/drivers/iris/iris_blorp.c
@@ -317,6 +317,10 @@ iris_blorp_exec(struct blorp_batch *blorp_batch,
params->y1 - params->y0, scale);
}
+#if GEN_GEN >= 12
+ genX(emit_aux_map_state)(batch);
+#endif
+
iris_handle_always_flush_cache(batch);
blorp_exec(blorp_batch, params);
diff --git a/src/gallium/drivers/iris/iris_context.c b/src/gallium/drivers/iris/iris_context.c
index 28f6be70df1..7859b72efdc 100644
--- a/src/gallium/drivers/iris/iris_context.c
+++ b/src/gallium/drivers/iris/iris_context.c
@@ -98,6 +98,7 @@ iris_lost_context_state(struct iris_batch *batch)
ice->state.current_hash_scale = 0;
memset(ice->state.last_grid, 0, sizeof(ice->state.last_grid));
batch->last_surface_base_address = ~0ull;
+ batch->last_aux_map_state = 0;
ice->vtbl.lost_genx_state(ice, batch);
}
diff --git a/src/gallium/drivers/iris/iris_genx_protos.h b/src/gallium/drivers/iris/iris_genx_protos.h
index 84d4b4b324c..6e9a7ba5f8e 100644
--- a/src/gallium/drivers/iris/iris_genx_protos.h
+++ b/src/gallium/drivers/iris/iris_genx_protos.h
@@ -41,6 +41,8 @@ void genX(update_pma_fix)(struct iris_context *ice,
struct iris_batch *batch,
bool enable);
+void genX(emit_aux_map_state)(struct iris_batch *batch);
+
/* iris_blorp.c */
void genX(init_blorp)(struct iris_context *ice);
diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c
index ac6a5dd5fd1..c56413b268d 100644
--- a/src/gallium/drivers/iris/iris_state.c
+++ b/src/gallium/drivers/iris/iris_state.c
@@ -98,6 +98,7 @@
#include "drm-uapi/i915_drm.h"
#include "nir.h"
#include "intel/compiler/brw_compiler.h"
+#include "intel/common/gen_aux_map.h"
#include "intel/common/gen_l3_config.h"
#include "intel/common/gen_sample_positions.h"
#include "iris_batch.h"
@@ -4989,6 +4990,30 @@ iris_viewport_zmin_zmax(const struct pipe_viewport_state *vp, bool halfz,
util_viewport_zmin_zmax(vp, halfz, zmin, zmax);
}
+#if GEN_GEN >= 12
+void
+genX(emit_aux_map_state)(struct iris_batch *batch)
+{
+ struct iris_screen *screen = batch->screen;
+ void *aux_map_ctx = iris_bufmgr_get_aux_map_context(screen->bufmgr);
+ if (!aux_map_ctx)
+ return;
+ uint32_t aux_map_state_num = gen_aux_map_get_state_num(aux_map_ctx);
+ if (batch->last_aux_map_state != aux_map_state_num) {
+ /* If the aux-map state number increased, then we need to rewrite the
+ * register. Rewriting the register is used to both set the aux-map
+ * translation table address, and also to invalidate any previously
+ * cached translations.
+ */
+ uint64_t base_addr = gen_aux_map_get_base(aux_map_ctx);
+ assert(base_addr != 0 && ALIGN(base_addr, 32 * 1024) == base_addr);
+ iris_load_register_imm64(batch, GENX(GFX_AUX_TABLE_BASE_ADDR_num),
+ base_addr);
+ batch->last_aux_map_state = aux_map_state_num;
+ }
+}
+#endif
+
static void
iris_upload_dirty_render_state(struct iris_context *ice,
struct iris_batch *batch,
@@ -5840,6 +5865,10 @@ iris_upload_dirty_render_state(struct iris_context *ice,
if (ice->state.current_hash_scale != 1)
genX(emit_hashing_mode)(ice, batch, UINT_MAX, UINT_MAX, 1);
+
+#if GEN_GEN >= 12
+ genX(emit_aux_map_state)(batch);
+#endif
}
static void
@@ -6092,6 +6121,10 @@ iris_upload_compute_state(struct iris_context *ice,
if (ice->state.need_border_colors)
iris_use_pinned_bo(batch, ice->state.border_color_pool.bo, false);
+#if GEN_GEN >= 12
+ genX(emit_aux_map_state)(batch);
+#endif
+
if (dirty & IRIS_DIRTY_CS) {
/* The MEDIA_VFE_STATE documentation for Gen8+ says:
*
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