Mesa (master): 47 new commits

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URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=d298740a1c1c7798d21a0978d6fa5f72ee97b9fe
Author: Nanley Chery <nanley.g.chery at intel.com>
Date:   Fri Aug 2 15:38:36 2019 -0700

    iris: Disallow incomplete resource creation
    
    If a modifier specifies an aux, it must be created.
    
    Fixes: 75a3947af46 ("iris/resource: Fall back to no aux if creation fails")
    Reviewed-by: Sagar Ghuge <sagar.ghuge at intel.com>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=f2fc5dece93019f0bab203247985cf350d541156
Author: Nanley Chery <nanley.g.chery at intel.com>
Date:   Wed Sep 25 12:48:57 2019 -0700

    iris: Don't leak the resource for unsupported modifier
    
    Make sure the res struct is free'd before returning.
    
    Fixes: 2dce0e94a3d ("iris: Initial commit of a new 'iris' driver for Intel Gen8+ GPUs.")
    Reviewed-by: Sagar Ghuge <sagar.ghuge at intel.com>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=7a619b5c759e9d1a9795d4d79c7746ec47a00431
Author: Nanley Chery <nanley.g.chery at intel.com>
Date:   Wed Aug 21 15:23:24 2019 -0700

    iris: Enable HIZ_CCS sampling
    
    Reviewed-by: Sagar Ghuge <sagar.ghuge at intel.com>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=8e7644e48f8122409faf558ad3252a515576d2f0
Author: Nanley Chery <nanley.g.chery at intel.com>
Date:   Wed Sep 18 09:44:02 2019 -0700

    intel/blorp: Satisfy clear color rules for HIZ_CCS
    
    Store the converted depth value into two dwords. Avoids regressing the
    piglit test "fbo-depth-array depth-clear", when HIZ_CCS sampling is
    enabled in a later commit.
    
    Reviewed-by: Sagar Ghuge <sagar.ghuge at intel.com>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=0aa308f4200ad88c9b9ac0fd3e2ad30bde74edb9
Author: Nanley Chery <nanley.g.chery at intel.com>
Date:   Wed Aug 21 10:57:29 2019 -0700

    intel: Fix and use HIZ_CCS write through mode
    
    Write through to the CCS if the surface is used as a texture and can be
    sampled by the HW with CCS.
    
    Reviewed-by: Sagar Ghuge <sagar.ghuge at intel.com>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=fee4dbcb4ddac04c132c5f69f67b76b5ddaeb793
Author: Nanley Chery <nanley.g.chery at intel.com>
Date:   Mon Oct 7 15:52:21 2019 -0700

    iris: Start using blorp_can_hiz_clear_depth()
    
    Check that the alignment requirements for HIZ_CCS are satisfied by using
    this function.
    
    Reviewed-by: Sagar Ghuge <sagar.ghuge at intel.com>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=5425fcf2cb39dc9df56593d4460b56688506c0cc
Author: Nanley Chery <nanley.g.chery at intel.com>
Date:   Mon Oct 7 15:53:44 2019 -0700

    intel/blorp: Satisfy HIZ_CCS fast-clear alignments
    
    Prevent the piglit test,
    amd_vertex_shader_layer-layered-depth-texture-render, from regressing in
    in a future commit.
    
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=6451008e8b6013351e3e7e26f6827a218a76fcb3
Author: Nanley Chery <nanley.g.chery at intel.com>
Date:   Mon Oct 7 15:48:33 2019 -0700

    intel: Refactor blorp_can_hiz_clear_depth()
    
    Prepare this function to be used in iris and to handle new Gen12 behavior.
    
    Reviewed-by: Sagar Ghuge <sagar.ghuge at intel.com>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=cc99d0adc0d40ba5879b0a1a1ec0b71df59fbe96
Author: Nanley Chery <nanley.g.chery at intel.com>
Date:   Thu Sep 19 13:10:24 2019 -0700

    isl: Add isl_surf_supports_hiz_ccs_wt()
    
    Add a helper to determine if an ISL surface supports the write-through
    mode of HIZ_CCS.
    
    Reviewed-by: Sagar Ghuge <sagar.ghuge at intel.com>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=6020ebf799187f7d1ad58e30d7e6d65747b0c539
Author: Nanley Chery <nanley.g.chery at intel.com>
Date:   Fri Aug 9 11:08:26 2019 -0700

    iris: Enable HIZ_CCS in depth buffer instructions
    
    Reviewed-by: Sagar Ghuge <sagar.ghuge at intel.com>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=af6ff488949a0f0339e1403199a326c5c08b771c
Author: Nanley Chery <nanley.g.chery at intel.com>
Date:   Thu Aug 8 17:39:47 2019 -0700

    iris: Define initial HIZ_CCS state and transitions
    
    Make it match those of HIZ.
    
    Reviewed-by: Sagar Ghuge <sagar.ghuge at intel.com>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=c991045d38ad0d4ccbd8b7355811b85341eda3a2
Author: Nanley Chery <nanley.g.chery at intel.com>
Date:   Wed Aug 7 16:02:51 2019 -0700

    iris: Create an unusable secondary aux surface
    
    The HIZ_CCS and MCS_CCS auxiliary surface modes require that drivers
    store information about two aux buffers. We choose to represent this as
    HiZ/MCS being the primary aux surface and the CCS as an secondary/extra
    aux surface. This representation has the effect of placing most of the
    code that will have to choose between the two aux surfaces around the
    aux-map entry points.
    
    Reviewed-by: Sagar Ghuge <sagar.ghuge at intel.com>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=909030bca664bd71b95d662afbfabdca3a9c4146
Author: Nanley Chery <nanley.g.chery at intel.com>
Date:   Thu Aug 1 16:49:57 2019 -0700

    iris: Don't guess the aux_usage
    
    Instead of guessing an aux_usage, then confirming it if the
    isl_surf_get_*_surf functions are successful, just call the ISL
    functions up-front. This will help us to more easily determine if a
    depth buffer supports HIZ_CCS.
    
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=04e5f7e8a9ecd7ffa6e5cd81317e53899e397f1c
Author: Nanley Chery <nanley.g.chery at intel.com>
Date:   Fri Aug 9 10:02:50 2019 -0700

    intel/blorp: Treat HIZ_CCS like HiZ
    
    Allow it in depth buffer instructions but disable it for blits.
    
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=cc415f911f7bbba683e4724af4ab58d8cc9523ca
Author: Nanley Chery <nanley.g.chery at intel.com>
Date:   Wed Aug 21 16:43:26 2019 -0700

    intel/blorp: Assert against HiZ in surface states
    
    Avoid unexpected behavior if the caller happens to pass in a HiZ aux
    usage.
    
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=c50f8b2fc94913a7c96468ba930091710147b302
Author: Nanley Chery <nanley.g.chery at intel.com>
Date:   Mon Aug 19 09:17:26 2019 -0700

    intel: Support HIZ_CCS in isl_surf_get_ccs_surf
    
    Add an extra aux parameter which will be filled out with CCS if the
    first two isl_surf parameters fit the requirements for HiZ_CCS.
    
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=e2e67b3f11bf11dedab77322a28c87c32d5ed30a
Author: Nanley Chery <nanley.g.chery at intel.com>
Date:   Wed Jul 31 14:38:29 2019 -0700

    isl: Reduce assertions during aux surf creation
    
    Return false more often to reduce the burden on the caller.
    
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=6670e07a6efb69951c45583b51d51de31c9e7119
Author: Nanley Chery <nanley.g.chery at intel.com>
Date:   Thu Aug 8 13:40:08 2019 -0700

    intel: Enable CCS_E for R24_UNORM_X8_TYPELESS on TGL+
    
    While this format isn't listed in BSpec: 53911, other documentation and
    empirical evidence suggest that it's fine to remap it to R32_FLOAT. I've
    filed a bug for the BSpec page.
    
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=f93bc14618ae22a3d3b8030be6ba58d589f0bab8
Author: Nanley Chery <nanley.g.chery at intel.com>
Date:   Fri Aug 9 17:18:48 2019 -0700

    intel: Use 3DSTATE_DEPTH_BUFFER::ControlSurfaceEnable
    
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=ab994ecae68511f5f08f5ab0b5d4da624de3f7d9
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Fri May 4 09:43:42 2018 -0700

    intel/isl: Support HIZ_CCS in emit_depth_stencil_hiz
    
    v2. Remove undocumented CCS_E-only mode for depth. (Nanley)
    
    Co-authored-by: Nanley Chery <nanley.g.chery at intel.com>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=6312328a61a372e78d246068ea0004868954a0aa
Author: Nanley Chery <nanley.g.chery at intel.com>
Date:   Fri Aug 9 18:04:58 2019 -0700

    intel: Use RENDER_SURFACE_STATE::DepthStencilResource
    
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=5d34a9975f47e8cd4f57c304f5e39ab6c7201603
Author: Jordan Justen <jordan.l.justen at intel.com>
Date:   Tue May 29 17:10:47 2018 -0700

    intel: Update alignment restrictions for HiZ surfaces.
    
    v2 (Nanley):
    * Maintain a chronological ordering for HiZ alignments. Suggested by
      Ken.
    
    Co-authored-by: Nanley Chery <nanley.g.chery at intel.com>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=6cd9731d96c4a48252b91881491aa43ba565bf95
Author: Nanley Chery <nanley.g.chery at intel.com>
Date:   Fri Aug 30 14:58:54 2019 -0700

    iris: Clear ::has_hiz when disabling aux
    
    Fixes: 2cddc953cd0 ("iris: some initial HiZ bits")
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=d5fb9cccdce2d44427582ca6d9201d5ec42fedb2
Author: Nanley Chery <nanley.g.chery at intel.com>
Date:   Thu Aug 15 10:17:11 2019 -0700

    intel/blorp: Disable depth testing for slow depth clears
    
    We'll start doing slow depth clears more often on HIZ_CCS buffers in a
    future commit. Reduce the performance impact by making them use less
    bandwidth.
    
    From the Depth Test section of the BSpec:
    
       This function is enabled by the Depth Test Enable state variable. If
       enabled, the pixel's ("source") depth value is first computed. After
       computation the pixel's depth value is clamped to the range defined
       by Minimum Depth and Maximum Depth in the selected CC_VIEWPORT state.
       Then the current ("destination") depth buffer value for this pixel is
       read.
    
    and from the Depth Buffer Updates section of the BSpec:
    
       If depth testing is disabled or the depth test passed, the incoming
       pixel's depth value is written to the Depth Buffer.
    
    Taken together, it's clear that depth testing isn't necessary to perform
    a depth buffer clear. Mark Janes and I analyzed this patch with
    frameretrace and a depthrange piglit test. I disabled HiZ to ensure we'd
    get slow depth clears. We've observed the bandwidth consumption by the
    depth buffer access to be cut ~50% on BDW and SKL during depth clears.
    On a more graphically intensive workload, the Shadowmapping Sascha
    benchmark, I took the average of 3 runs on a BDW with a display
    resolution of about 1920x1200 (minus some desktop environment
    decorations). I measured a 22.61% FPS improvement when HiZ is disabled.
    
    v2. The BSpec doesn't mandate this behavior, update comment accordingly.
        (Ken)
    
    Fixes: bc4bb5a7e30 ("intel/blorp: Emit more complete DEPTH_STENCIL state")
    Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=e655eed53190306c0391fc5e88cd0ca8df4948ea
Author: Nanley Chery <nanley.g.chery at intel.com>
Date:   Mon Mar 25 14:15:01 2019 -0700

    intel: Enable CCS_E for some formats on Gen12
    
    In ISL:
       Update the format table to add CCS_E support for some 8BPP formats,
       some 16BPP formats, and R10G10B10A2_UNORM_SRGB.
    
       In the helper for determining CCS_E support, we return false for some
       16BPP formats because they aren't properly handled in blorp_copy().
    
    In BLORP:
       Allow the new and non-problematic formats for CCS_E-enabled copies.
    
    v2. Update other fields for A1B5G5R5_UNORM and A4B4G4R4_UNORM in table.
    
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
    Reviewed-by: Jordan Justen <jordan.l.justen at intel.com> (v1)

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=126c9562d98bf84b19140e318758ac0d4b0a9b5f
Author: Nanley Chery <nanley.g.chery at intel.com>
Date:   Tue Mar 19 18:23:46 2019 -0700

    isl: Redefine the CCS layout for Gen12
    
    The CCS could be described in a number of ways, but this format was
    chosen to minimize churn in the drivers. We may decide on an different
    direction in the future.
    
    v2. Increase alignment for display surfaces. (Nanley)
    
    Reviewed-by: Jordan Justen <jordan.l.justen at intel.com> (v1)
    Acked-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=1e91280242d266758a0c59b5c2575d7d78ebfb91
Author: Nanley Chery <nanley.g.chery at intel.com>
Date:   Mon Jan 14 11:32:21 2019 -0800

    isl: Add and use isl_tiling_flag_to_enum()
    
    Use a helper that will automatically handle Gen12's CCS tiling when
    creating a CCS isl_surf.
    
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
    Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=82822bc5497c2cf4643204d12cd0ed3f96ae72e1
Author: Nanley Chery <nanley.g.chery at intel.com>
Date:   Mon Aug 12 15:41:11 2019 -0700

    iris: Allow for non-Y-tiled aux allocation
    
    The Gen12 CCS is not Y-tiled.
    
    Reviewed-by: Sagar Ghuge <sagar.ghuge at intel.com>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
    Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=22be1447bb46b4dc63fbc2cfc696c01a0f90ab0e
Author: Nanley Chery <nanley.g.chery at intel.com>
Date:   Wed Mar 27 14:40:58 2019 -0700

    isl/drm: Map HiZ and CCS tilings to Y
    
    In the function which translates ISL tilings to i915 tilings, map ISL's
    HiZ and CCS tilings to Y instead of NONE (linear). The HW docs describe
    HiZ and pre-Gen12 CCS surfaces as being Y-tiled in memory.
    
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
    Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=901bed51227b1d3a186891068f29623b757ff2f2
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Fri May 4 09:44:24 2018 -0700

    intel/isl: Update surf_fill_state for gen12
    
    v2 (Nanley):
    * Avoid driver churn for now.
    * Include some media compression changes.
    
    Co-authored-by: Nanley Chery <nanley.g.chery at intel.com>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
    Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=caf4cc548eb20b1c8996287ba622c6846cd1e298
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Fri May 4 09:34:52 2018 -0700

    intel/isl/fill_state: Separate aux_mode handling from aux_surf
    
    v2. Avoid driver churn for now. (Nanley)
    
    Co-authored-by: Nanley Chery <nanley.g.chery at intel.com>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
    Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=a1e0b210612b040c0308ca35f5417d6dbf650085
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Fri May 4 09:43:01 2018 -0700

    intel/isl: Add new aux modes available on gen12
    
    v2. Add media compression. (Nanley)
    
    Co-authored-by: Nanley Chery <nanley.g.chery at intel.com>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
    Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=77f506382f903cda54dddac4a96717e815aacbb9
Author: Nanley Chery <nanley.g.chery at intel.com>
Date:   Thu Sep 26 17:23:33 2019 -0700

    i965/miptree: Avoid -Wswitch for the Gen12 aux modes
    
    Avoid the compiler warnings for the new enums that will be introduced in
    a future commit.
    
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
    Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=8af1853331254c50476e424d41efa76d2e86c0e9
Author: Nanley Chery <nanley.g.chery at intel.com>
Date:   Fri Sep 13 14:18:42 2019 -0700

    anv/private: Modify aux slice helpers for Gen12 CCS
    
    The isl_surf structs for Gen12's CCS won't describe how many slices in
    the main surface can be compressed. All slices will be compressable if
    CCS is enabled, so lookup the main surface's logical dimension.
    
    v2. Add a space before a `?`. (Jordan)
    
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
    Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=ba52cd7ab2a6908eb198307186e9c5ece004450a
Author: Nanley Chery <nanley.g.chery at intel.com>
Date:   Fri Aug 30 14:16:54 2019 -0700

    intel/blorp: Don't assert aux slices match main slices
    
    This isn't accurate enough for HiZ which can have a discontiguous range
    of supported aux slices. This also won't work with the plan to represent
    Gen12 CCS as a single slice surface.
    
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
    Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=4021a3925c780643e0b402c5b20ddf7b6b780c09
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Tue May 15 15:57:39 2018 -0700

    intel/blorp: Use surf instead of aux_surf for image dimensions
    
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
    Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=d90bffaef8b0ff3bc8736a1ac30afe7390eeac29
Author: Nanley Chery <nanley.g.chery at intel.com>
Date:   Thu May 9 16:38:12 2019 -0700

    intel/blorp: Halve the Gen12 fast-clear/resolve rectangle
    
    Update their dimensions according to the Bspec.
    
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
    Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=43b48ee752eb733c7d3c4e3146c5ba1bdcec42a7
Author: Rafael Antognolli <rafael.antognolli at intel.com>
Date:   Wed Apr 24 13:05:20 2019 -0700

    intel/blorp/gen12: Set FWCC when storing the clear color.
    
    From "Render Target Fast Clear" description for Gen12:
    
       "SW must store clear color using MI_STORE_DATA_IMM with
       ForceWriteCompletionCheck bit set."
    
    From Instruction_MI_STORE_DATA_IMM, bitfield 10 (when set to 1):
    
       "Following the last write from this command, Command Streamer
       will wait for all previous writes are completed and in global
       observable domain before moving to next command."
    
    We use 4 SDIs to store the clear color (one per channel). From the
    description, it looks to me that setting that flag only on the last SDI
    should be enough.
    
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
    Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=07e16221d975bbc286e89bffadf60f36afcddb7f
Author: Nanley Chery <nanley.g.chery at intel.com>
Date:   Tue Apr 23 15:28:18 2019 -0700

    isl: Round up some pitches to 512B for Gen12's CCS
    
    Gen12's CCS requires that the main surface have a pitch aligned to 512B.
    
    v2. Provide a BSpec citation. (Ken)
    
    Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=f6aefa94cc83c92e0ed18aea16e63254a0ba4c30
Author: Nanley Chery <nanley.g.chery at intel.com>
Date:   Tue Sep 17 09:16:12 2019 -0700

    iris: Don't assume CCS_E includes CCS_D
    
    There's no longer a clear-only compression mode of CCS on Gen12+.
    
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
    Reviewed-by: Sagar Ghuge <sagar.ghuge at intel.com>
    Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=300d77c2fa5427f7482eea42af785d3743eb113f
Author: Nanley Chery <nanley.g.chery at intel.com>
Date:   Tue Sep 17 09:16:12 2019 -0700

    anv/cmd_buffer: Don't assume CCS_E includes CCS_D
    
    There's no longer a clear-only compression mode of CCS on Gen12+.
    
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=4f0b5f9732b144f9f0d6a577e10d2896cb3a4f3c
Author: Nanley Chery <nanley.g.chery at intel.com>
Date:   Fri Sep 14 11:25:43 2018 -0700

    anv/image: Disable CCS_D on Gen12+
    
    Clear-only compression no longer exists on TGL.
    
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
    Reviewed-by: Sagar Ghuge <sagar.ghuge at intel.com>
    Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=a94cb6503f88c81cf95227702f88e29944ec4766
Author: Nanley Chery <nanley.g.chery at intel.com>
Date:   Fri Aug 9 10:41:38 2019 -0700

    isl: Disable CCS_D on Gen12+
    
    Clear-only compression no longer exists on TGL.
    
    v2. Add BSpec reference. (Sagar)
    
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
    Reviewed-by: Sagar Ghuge <sagar.ghuge at intel.com>
    Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=83fc15e5ba4be270345ea26126f7ae0471f0e70d
Author: Nanley Chery <nanley.g.chery at intel.com>
Date:   Mon Sep 23 11:09:46 2019 -0700

    iris: Drop support for I915_FORMAT_MOD_Y_TILED_CCS on TGL+
    
    The format of the CCS has changed.
    
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
    Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=0eaf293b47966576b21aa28ddf74de27669210c6
Author: Nanley Chery <nanley.g.chery at intel.com>
Date:   Mon Sep 23 13:32:06 2019 -0700

    anv/formats: Disable I915_FORMAT_MOD_Y_TILED_CCS on TGL+
    
    The format of the CCS has changed.
    
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
    Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=d0fcc2dd503f734f10f879ad666c27fd81c44262
Author: Nanley Chery <nanley.g.chery at intel.com>
Date:   Mon Oct 21 12:56:00 2019 -0700

    anv: Properly allocate aux-tracking space for CCS_E
    
    add_aux_state_tracking_buffer() actually checks the aux usage when
    determining how many dwords to allocate for state tracking. Move the
    function call to the point after the CCS_E aux usage is assigned.
    
    Fixes: de3be618016 ("anv/cmd_buffer: Rework aux tracking")
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=698d723a6d4f19de750fafc9287f1bd74f25ba07
Author: Nanley Chery <nanley.g.chery at intel.com>
Date:   Wed Oct 23 15:51:56 2019 -0700

    anv/blorp: Use BLORP_BATCH_NO_UPDATE_CLEAR_COLOR
    
    Avoid failing the `info->use_clear_address` assertion in ISL on Gen12+.
    
    Fixes: 6c9f9a82d78 ("intel/genxml,isl: Add gen12 render surface state changes")
    Reported-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>