Mesa (master): intel/genxml: Add gen12 tile cache flush bit

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Module: Mesa
Branch: master
Commit: f573cd4757355c5ffe66c90ad6e08265865ec730
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=f573cd4757355c5ffe66c90ad6e08265865ec730

Author: Jordan Justen <jordan.l.justen at intel.com>
Date:   Fri Sep  8 19:08:21 2017 -0700

intel/genxml: Add gen12 tile cache flush bit

Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>

---

 src/intel/genxml/gen12.xml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/intel/genxml/gen12.xml b/src/intel/genxml/gen12.xml
index 98e75c24b43..98fbf7d9180 100644
--- a/src/intel/genxml/gen12.xml
+++ b/src/intel/genxml/gen12.xml
@@ -6364,6 +6364,7 @@
       <value name="GGTT" value="1"/>
     </field>
     <field name="Flush LLC" start="58" end="58" type="bool"/>
+    <field name="Tile Cache Flush Enable" start="60" end="60" type="bool"/>
     <field name="Address" start="66" end="111" type="address"/>
     <field name="Immediate Data" start="128" end="191" type="uint"/>
   </instruction>