Mesa (master): anv: Move the RT BTI flush workaround to begin_subpass

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Module: Mesa
Branch: master
Commit: f60ef0fff4b99c0caf9ae4f0f17637372cf9cd7a
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=f60ef0fff4b99c0caf9ae4f0f17637372cf9cd7a

Author: Jason Ekstrand <jason at jlekstrand.net>
Date:   Wed Oct 30 15:05:29 2019 -0500

anv: Move the RT BTI flush workaround to begin_subpass

Now that we're no longer compacting binding table entries, the only time
they can possibly change is when we actually switch subpasses.

Reviewed-by: Rafael Antognolli <rafael.antognolli at intel.com>

---

 src/intel/vulkan/genX_cmd_buffer.c | 41 +++++++++++++++++---------------------
 1 file changed, 18 insertions(+), 23 deletions(-)

diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c
index 12ab52e33a6..6e42b659f4c 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -2375,29 +2375,6 @@ emit_binding_table(struct anv_cmd_buffer *cmd_buffer,
       bt_map[s] = surface_state.offset + state_offset;
    }
 
-#if GEN_GEN >= 11
-   /* The PIPE_CONTROL command description says:
-    *
-    *    "Whenever a Binding Table Index (BTI) used by a Render Taget Message
-    *     points to a different RENDER_SURFACE_STATE, SW must issue a Render
-    *     Target Cache Flush by enabling this bit. When render target flush
-    *     is set due to new association of BTI, PS Scoreboard Stall bit must
-    *     be set in this packet."
-    *
-    * FINISHME: Currently we shuffle around the surface states in the binding
-    * table based on if they are getting used or not. So, we've to do below
-    * pipe control flush for every binding table upload. Make changes so
-    * that we do it only when we modify render target surface states.
-    */
-   anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
-      pc.RenderTargetCacheFlushEnable  = true;
-      pc.StallAtPixelScoreboard        = true;
-#if GEN_GEN >= 12
-      pc.TileCacheFlushEnable = true;
-#endif
-   }
-#endif
-
    return VK_SUCCESS;
 }
 
@@ -4564,6 +4541,24 @@ cmd_buffer_begin_subpass(struct anv_cmd_buffer *cmd_buffer,
    }
 
    cmd_buffer_emit_depth_stencil(cmd_buffer);
+
+#if GEN_GEN >= 11
+   /* The PIPE_CONTROL command description says:
+    *
+    *    "Whenever a Binding Table Index (BTI) used by a Render Taget Message
+    *     points to a different RENDER_SURFACE_STATE, SW must issue a Render
+    *     Target Cache Flush by enabling this bit. When render target flush
+    *     is set due to new association of BTI, PS Scoreboard Stall bit must
+    *     be set in this packet."
+    */
+   anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
+      pc.RenderTargetCacheFlushEnable  = true;
+      pc.StallAtPixelScoreboard        = true;
+#if GEN_GEN >= 12
+      pc.TileCacheFlushEnable = true;
+#endif
+   }
+#endif
 }
 
 static enum blorp_filter