Mesa (master): ac/surface: add RADEON_SURF_NO_FMASK
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Tue Sep 10 03:44:12 UTC 2019
Module: Mesa
Branch: master
Commit: 7d4a10a29f6f667f2a4a89ebc87df4c01ccb3597
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7d4a10a29f6f667f2a4a89ebc87df4c01ccb3597
Author: Marek Olšák <marek.olsak at amd.com>
Date: Tue Aug 27 20:29:11 2019 -0400
ac/surface: add RADEON_SURF_NO_FMASK
This controls FMASK and CMASK computation for MSAA.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
---
src/amd/common/ac_surface.c | 11 +++++++----
src/amd/common/ac_surface.h | 1 +
src/gallium/drivers/radeonsi/si_texture.c | 9 +++------
src/gallium/winsys/radeon/drm/radeon_drm_surface.c | 5 +++--
4 files changed, 14 insertions(+), 12 deletions(-)
diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index 5cfd192118d..2c2917d4a23 100644
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -488,7 +488,8 @@ static void ac_compute_cmask(const struct radeon_info *info,
unsigned num_pipes = info->num_tile_pipes;
unsigned cl_width, cl_height;
- if (surf->flags & RADEON_SURF_Z_OR_SBUFFER)
+ if (surf->flags & RADEON_SURF_Z_OR_SBUFFER ||
+ (config->info.samples >= 2 && !surf->fmask_size))
return;
assert(info->chip_class <= GFX8);
@@ -850,7 +851,8 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
}
/* Compute FMASK. */
- if (config->info.samples >= 2 && AddrSurfInfoIn.flags.color) {
+ if (config->info.samples >= 2 && AddrSurfInfoIn.flags.color &&
+ !(surf->flags & RADEON_SURF_NO_FMASK)) {
ADDR_COMPUTE_FMASK_INFO_INPUT fin = {0};
ADDR_COMPUTE_FMASK_INFO_OUTPUT fout = {0};
ADDR_TILEINFO fmask_tile_info = {};
@@ -1292,7 +1294,7 @@ static int gfx9_compute_miptree(ADDR_HANDLE addrlib,
}
/* FMASK */
- if (in->numSamples > 1) {
+ if (in->numSamples > 1 && !(surf->flags & RADEON_SURF_NO_FMASK)) {
ADDR2_COMPUTE_FMASK_INFO_INPUT fin = {0};
ADDR2_COMPUTE_FMASK_INFO_OUTPUT fout = {0};
@@ -1350,7 +1352,8 @@ static int gfx9_compute_miptree(ADDR_HANDLE addrlib,
/* CMASK -- on GFX10 only for FMASK */
if (in->swizzleMode != ADDR_SW_LINEAR &&
- (info->chip_class <= GFX9 || in->numSamples > 1)) {
+ ((info->chip_class <= GFX9 && in->numSamples == 1) ||
+ (surf->fmask_size && in->numSamples >= 2))) {
ADDR2_COMPUTE_CMASK_INFO_INPUT cin = {0};
ADDR2_COMPUTE_CMASK_INFO_OUTPUT cout = {0};
diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h
index ca577b6e5db..53074c90faf 100644
--- a/src/amd/common/ac_surface.h
+++ b/src/amd/common/ac_surface.h
@@ -71,6 +71,7 @@ enum radeon_micro_mode {
#define RADEON_SURF_SHAREABLE (1 << 26)
#define RADEON_SURF_NO_RENDER_TARGET (1 << 27)
#define RADEON_SURF_FORCE_SWIZZLE_MODE (1 << 28)
+#define RADEON_SURF_NO_FMASK (1 << 29)
struct legacy_surf_level {
uint64_t offset;
diff --git a/src/gallium/drivers/radeonsi/si_texture.c b/src/gallium/drivers/radeonsi/si_texture.c
index 64fcd50f3a1..1f7cab6b2f3 100644
--- a/src/gallium/drivers/radeonsi/si_texture.c
+++ b/src/gallium/drivers/radeonsi/si_texture.c
@@ -315,6 +315,8 @@ static int si_init_surface(struct si_screen *sscreen,
flags |= RADEON_SURF_IMPORTED | RADEON_SURF_SHAREABLE;
if (!(ptex->flags & SI_RESOURCE_FLAG_FORCE_MSAA_TILING))
flags |= RADEON_SURF_OPTIMIZE_FOR_SPACE;
+ if (sscreen->debug_flags & DBG(NO_FMASK))
+ flags |= RADEON_SURF_NO_FMASK;
if (sscreen->info.chip_class >= GFX10 &&
(ptex->flags & SI_RESOURCE_FLAG_FORCE_MSAA_TILING)) {
@@ -1369,9 +1371,7 @@ si_texture_create_object(struct pipe_screen *screen,
si_texture_allocate_htile(sscreen, tex);
}
} else {
- if (base->nr_samples > 1 &&
- !buf &&
- !(sscreen->debug_flags & DBG(NO_FMASK))) {
+ if (tex->surface.fmask_size) {
/* Allocate FMASK. */
tex->fmask_offset = align64(tex->size,
tex->surface.fmask_alignment);
@@ -1382,9 +1382,6 @@ si_texture_create_object(struct pipe_screen *screen,
tex->size = tex->cmask_offset + tex->surface.cmask_size;
tex->cb_color_info |= S_028C70_FAST_CLEAR(1);
tex->cmask_buffer = &tex->buffer;
-
- if (!tex->surface.fmask_size || !tex->surface.cmask_size)
- goto error;
}
/* Shared textures must always set up DCC here.
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_surface.c b/src/gallium/winsys/radeon/drm/radeon_drm_surface.c
index d33c4c7132d..e09805784e0 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_surface.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_surface.c
@@ -307,7 +307,7 @@ static int radeon_winsys_surface_init(struct radeon_winsys *rws,
/* Compute FMASK. */
if (ws->gen == DRV_SI &&
tex->nr_samples >= 2 &&
- !(flags & (RADEON_SURF_Z_OR_SBUFFER | RADEON_SURF_FMASK))) {
+ !(flags & (RADEON_SURF_Z_OR_SBUFFER | RADEON_SURF_FMASK | RADEON_SURF_NO_FMASK))) {
/* FMASK is allocated like an ordinary texture. */
struct pipe_resource templ = *tex;
struct radeon_surf fmask = {};
@@ -351,7 +351,8 @@ static int radeon_winsys_surface_init(struct radeon_winsys *rws,
surf_ws->u.legacy.fmask.pitch_in_pixels = fmask.u.legacy.level[0].nblk_x;
}
- if (ws->gen == DRV_SI) {
+ if (ws->gen == DRV_SI &&
+ (tex->nr_samples <= 1 || surf_ws->fmask_size)) {
struct ac_surf_config config;
/* Only these fields need to be set for the CMASK computation. */
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