Mesa (master): 26 new commits
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Tue Sep 17 21:00:56 UTC 2019
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f55f7b199d135e8e174150eb09099535843adf6a
Author: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Date: Wed Feb 13 13:50:01 2019 +0100
docs/relnotes: add support for VK_KHR_shader_float_controls on Intel
v2:
- Move to 19.2.0 release notes (Andres).
v3:
- Move to 19.3.0 release notes (Andres).
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Signed-off-by: Andres Gomez <agomez at igalia.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f5dd6dfe012666123bb59b9a4f8e9afb46d67414
Author: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Date: Thu May 31 11:44:21 2018 +0200
anv: enable VK_KHR_shader_float_controls and SPV_KHR_float_controls
This adds support for
VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FLOAT_CONTROLS_PROPERTIES_KHR and
enables de Vulkan and SPIR-V extensions.
Also, notice that this includes the updates applied to the
VkPhysicalDeviceFloatControlsPropertiesKHR structure in the extension
VK_KHR_shader_float_controls v4 and Vulkan 1.1.116.
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Signed-off-by: Andres Gomez <agomez at igalia.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9b07020a4f2d6e680c89ef0a97dbb0bb53c5f299
Author: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Date: Mon Nov 19 12:38:10 2018 +0100
i965/fs: add support for shader float control to remove_extra_rounding_modes()
The remove_extra_rounding_modes() optimization will remove duplicated
rounding mode changes.
v2:
- Fix bug in the rounding mode change (Alejandro).
v3:
- Fix rounding modes.
v4:
- Updated to renamed shader info member and enum values (Andres).
v5:
- Simplify flags logic operations (Caio).
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Signed-off-by: Andres Gomez <agomez at igalia.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9bd88d10d82c15960e3936423c17dd6e0746e9ef
Author: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Date: Wed Feb 13 10:42:05 2019 +0100
i965/fs: set rounding mode when emitting nir_op_f2f32 or nir_op_f2f16
v2:
- Consider nir_op_f2f16 case too (Caio).
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Signed-off-by: Andres Gomez <agomez at igalia.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ba1e25e1aa63023040df3345146644b417953826
Author: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Date: Tue Feb 12 16:13:59 2019 +0100
i965/fs: set rounding mode when emitting fadd, fmul and ffma instructions
v2:
- Updated to renamed shader info member (Andres).
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Signed-off-by: Andres Gomez <agomez at igalia.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9da56ffc5228ff4578d4a078e456a0bf8588e71c
Author: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Date: Fri Jun 1 12:36:47 2018 +0200
i965/fs: add emit_shader_float_controls_execution_mode() and aux functions
We need this function to emit code that setups the control register
later with the defined execution mode for the shader. Therefore, we
emit it as the first instruction.
v2:
- Fix bug in setting the default mode mask in brw_rnd_mode_from_nir().
- Fix support for rounding modes in brw_rnd_mode_from_nir().
v3:
- Updated to renamed shader info member and enum values (Andres).
v4:
- Add actual emission as first instruction of emit_nir_code (Caio).
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Signed-off-by: Andres Gomez <agomez at igalia.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8a6507b6fe03c13224d0409df00bdcd210e2a9a4
Author: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Date: Fri Sep 13 01:38:06 2019 +0300
i965/fs/generator: add new opcode to set float controls modes in control register
Before this commit, we had only FPRoundingMode decoration (the per
instruction one) that is applied during the SPIR-V handling. In
vtn_alu we find out the rounding mode, and generate the code
accordingly that later will be used to look for the respective
nir_op_f2f16_{rtz,rtne}.
Per-instruction gets prioritized because we make them explicit
conversions (with RTZ or RTNE nir opcodes) and they will override the
default execution mode defined with float controls. However, we need
to come back to the mode defined by float controls after the execution
of the FP Rounding instruction.
Therefore, the new SHADER_OPCODE_FLOAT_CONTROL_MODE opcode will be
used to set the default rounding mode and denorms treatment in the
whole shader while the pre-existent SHADER_OPCODE_RND_MODE, will be
used as prioritized rounding mode in a per-instruction basis.
v2:
- Fix bug in defining BRW_CR0_FP_MODE_MASK.
v3:
- Update comment (Caio).
v4:
- Split the patch into the helper and the new opcode (this
one) (Caio).
v5:
- Add an explanation on the actual purpose and priority of the newly
introduced opcode in the commit log (Caio).
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=28da9558f50a4b015799cf128c5914c9c5e93862
Author: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Date: Fri Sep 13 01:34:35 2019 +0300
i965/fs/generator: refactor rounding mode helper in preparation for float controls
v2:
- Fix bug in defining BRW_CR0_FP_MODE_MASK.
v3:
- Update comment (Caio).
v4:
- Split the patch into the helper (this one) and the new
opcode (Caio).
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=cdace5b0c65df29c65aa349158264bffa4147db9
Author: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Date: Mon Jul 9 10:32:10 2018 +0200
i965/fs/nir: add nir_op_unpack_half_2x16_split_*_flush_to_zero
The denorm mode is set in the control register, no need to do
something else.
v2:
- Add an assert to make sure that we realize if this assumption is
broken in the future (Caio).
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Signed-off-by: Andres Gomez <agomez at igalia.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3c474f851313db5318d727d017b763ea2cb01e6d
Author: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Date: Tue Dec 4 16:41:36 2018 +0100
intel/nir: do not apply the fsin and fcos trig workarounds for consts
If we have fsin or fcos trigonometric operations with constant values
as inputs, we will multiply the result by 0.99997 in
brw_nir_apply_trig_workarounds, making the result wrong.
Adjusting the rules so they do not apply to const values we let a
later constant fold to deal with it.
v2:
- Do not early constant fold but only apply the trig workaround for
non constants (Caio).
- Add fixes tag to commit log (Caio).
Fixes: bfd17c76c12 "i965: Port INTEL_PRECISE_TRIG=1 to NIR."
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Signed-off-by: Andres Gomez <agomez at igalia.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=dba4d0a319f6938263e362a44201ed1099353cac
Author: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Date: Tue Jul 10 13:17:05 2018 +0200
nir: fix fmin/fmax support for doubles
Until now, it was using the floating point version of fmin/fmax,
instead of the double version.
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2abc6299bfa29d905046c7d198e3262fb19c0119
Author: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Date: Tue Jul 10 12:04:38 2018 +0200
nir: fix denorm flush-to-zero in sqrt's lowering at nir_lower_double_ops
v2:
- Replace hard coded value with DBL_MIN (Connor).
v3:
- Have into account the FLOAT_CONTROLS_DENORM_PRESERVE_FP64
flag (Caio).
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Signed-off-by: Andres Gomez <agomez at igalia.com>
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com> [v2]
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1e0e3ed15a8cfb98a182714bcb3e55cfab5c3df7
Author: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Date: Mon Jul 9 09:46:59 2018 +0200
nir: fix denorms in unpack_half_1x16()
According to VK_KHR_shader_float_controls:
"Denormalized values obtained via unpacking an integer into a vector
of values with smaller bit width and interpreting those values as
floating-point numbers must: be flushed to zero, unless the entry
point is declared with the code:DenormPreserve execution mode."
v2:
- Add nir_op_unpack_half_2x16_flush_to_zero opcode (Connor).
v3:
- Adapt to use the new NIR lowering framework (Andres).
v4:
- Updated to renamed shader info member and enum values (Andres).
v5:
- Simplify flags logic operations (Caio).
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Signed-off-by: Andres Gomez <agomez at igalia.com>
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com> [v2]
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f097247dd831da9b6e48baebc8b91efec3afcd28
Author: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Date: Wed Dec 12 16:29:13 2018 +0100
nir/algebraic: disable inexact optimizations depending on float controls execution mode
If FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE or
FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO are enabled, do not apply the
inexact optimizations so the VK_KHR_shader_float_controls execution
mode is respected.
v2:
- Do not apply inexact optimizations if SHADER_DENORM_FLUSH_TO_ZERO is
enabled (Andres).
v3:
- Updated to renamed shader info member (Andres).
v4:
- Directly access execution mode instead of dragging it by parameter (Caio).
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Signed-off-by: Andres Gomez <agomez at igalia.com>
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com> [v1]
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3f782cdd2591259e120b76aa4891c305cc1e8cb6
Author: Andres Gomez <agomez at igalia.com>
Date: Tue Apr 23 15:54:24 2019 +0200
nir/algebraic: mark float optimizations returning one parameter as inexact
With the arrival of VK_KHR_shader_float_controls algebraic
optimizations for float types of the form (('fop', a, b), a) become
inexact depending on the execution mode.
For example, if we have activated SHADER_DENORM_FLUSH_TO_ZERO, in case
of a denorm value for the "a" parameter, we cannot return it still as
a denorm, it needs to be flushed to zero. Therefore, we mark now all
those operations as inexact.
Suggested-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Signed-off-by: Andres Gomez <agomez at igalia.com>
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5e22f3e29a21eb4623759b517619543f3553caea
Author: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Date: Mon Feb 4 15:10:35 2019 +0100
nir/constant_expressions: mind rounding mode converting from float to float16 destinations
v2:
- Move the op-code specific knowledge to nir_opcodes.py even if it
means a rount trip conversion (Connor).
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Signed-off-by: Andres Gomez <agomez at igalia.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ef681cf9713664bcd3e95d54cc158b93b3542dc8
Author: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Date: Sun Apr 21 12:35:17 2019 +0200
nir/opcodes: make sure f2f16_rtz and f2f16_rtne behavior is not overriden by the float controls execution mode
Suggested-by: Connor Abbott <cwabbott0 at gmail.com>
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Signed-off-by: Andres Gomez <agomez at igalia.com>
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7580707345b7df0f262935c30b43bde16d297e39
Author: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Date: Tue Feb 12 15:43:10 2019 +0100
nir: mind rounding mode on fadd, fsub, fmul and fma opcodes
According to Vulkan spec, the new execution modes affect only
correctly rounded SPIR-V instructions, which includes fadd, fsub and
fmul.
v2:
- Fix fmul, fsub and fadd round-to-zero definitions, they should use
auxiliary functions to calculate the proper value because Mesa uses
round-to-nearest-even rounding mode by default (Connor).
v3:
- Do an actual fused multiply-add at ffma (Connor).
v4:
- Simplify fadd and fmul for bit sizes < 64 (Connor).
- Do not use double ffma for 32 bits float (Connor).
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Signed-off-by: Andres Gomez <agomez at igalia.com>
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com> [v3]
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0ac07c7ca7207f3f1388c0450b456ecc578d9c5b
Author: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Date: Wed Feb 13 10:31:37 2019 +0100
nir: add support for round to zero rounding mode to nir_op_f2f32
f2f16's rounding modes are already handled and f2f64 don't need it
as there is not a floating point type with higher bit size than 64 for
now.
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5308333e789e19956172d4e77e7ae4cf2fb4eafb
Author: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Date: Thu Sep 6 16:01:34 2018 +0200
util: add fp64 -> fp32 conversion support for RTNE and RTZ rounding modes
In order to be coherent with the pre-existent API for half floats,
this new API for double is the one meant to be used when doing double
to float conversions. It is no more than a wrapper for the softfloat.h
API but we meant to keep that one private.
v2:
- Fix bug in _mesa_double_to_float_rtz() in the inf/nan detection
using the exponent value.
v3:
- Replace custom f64 -> f32 implementations with the softfloat
one (Andres).
v4:
- Added API usage clarifying comments (Caio).
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Signed-off-by: Andres Gomez <agomez at igalia.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=733ede8ff6c107ff2acb2dc6ba647d3ad2b3b6dc
Author: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Date: Wed Jul 4 12:02:30 2018 +0200
util: add float to float16 conversions with RTZ and RTNE
In order to be coherent with the pre-existent functions, this new API
is the one meant to be used when doing half float to float
conversions. It is no more than a wrapper for the softfloat.h API but
we meant to keep that one private.
v2:
- Replace custom f32 -> f16 RTZ implementation with the softfloat
one (Andres).
v3:
- Added API usage clarifying comments (Caio).
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Signed-off-by: Andres Gomez <agomez at igalia.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=153c714f2af932e7681627a4c7c9f3521d686100
Author: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Date: Tue Feb 12 09:51:31 2019 +0100
util: add softfloat functions to operate with doubles and floats
Implemented fadd, fsub, fmul and ffma for doubles and ffma for floats,
rounding to zero, using a modified implementation from Berkely
Softfloat 3e Library.
Their implementation correctness has been checked with the Berkeley
TestFloat Release 3e tool for x86_64.
v2:
- Reuse util_last_bit64() in _mesa_count_leading_zeros64()
implementation (Connor).
v3:
- Add a specific ffma for floats version (Connor).
- Implement the ffma for doubles version (Andres).
- Lots of fixes in fadd, fsub and fmul (Andres).
- Improved documentation (Andres).
v4:
- Added f64 -> f32 conversion function (Andres).
- Added f32 -> f16 RTZ conversion function (Andres).
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Signed-off-by: Andres Gomez <agomez at igalia.com>
Tested-by: Andres Gomez <agomez at igalia.com>
Acked-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f7d73db353e5b6416c98a8c05c585ea79b3eada2
Author: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Date: Wed Jun 20 09:11:14 2018 +0200
nir: add support for flushing to zero denorm constants
v2:
- Refactor conditions and shared function (Connor).
- Move code to nir_eval_const_opcode() (Connor).
- Don't flush to zero on fquantize2f16
From Vulkan spec, VK_KHR_shader_float_controls section:
"3) Do denorm and rounding mode controls apply to OpSpecConstantOp?
RESOLVED: Yes, except when the opcode is OpQuantizeToF16."
v3:
- Fix bit size (Connor).
- Fix execution mode on nir_loop_analize (Connor).
v4:
- Adapt after API changes to nir_eval_const_opcode (Andres).
v5:
- Simplify constant_denorm_flush_to_zero (Caio).
v6:
- Adapt after API changes and to use the new constant
constructors (Andres).
- Replace MAYBE_UNUSED with UNUSED as the first is going
away (Andres).
v7:
- Adapt to newly added calls (Andres).
- Simplified the auxiliary to flush denorms to zero (Caio).
- Updated to renamed supported capabilities member (Andres).
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Signed-off-by: Andres Gomez <agomez at igalia.com>
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com> [v4]
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=45668a8be112878a2d34a6ba11684b0ff60df4ed
Author: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Date: Fri Feb 1 11:23:28 2019 +0100
nir: add auxiliary functions to detect if a mode is enabled
v2:
- Added more functions.
v3:
- Simplify most of the functions (Caio).
v4:
- Updated to renamed enum values (Andres).
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Signed-off-by: Andres Gomez <agomez at igalia.com>
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com> [v2]
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com> [v3]
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=84781e1f1d8f68248bd39f817e4bc6dac3944320
Author: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Date: Thu May 31 12:20:30 2018 +0200
spirv/nir: keep track of SPV_KHR_float_controls execution modes
v2:
- Add support for rounding modes for each floating point bit size.
v3:
- Commit e68871f6a44 ("spirv: Handle constants and types before
execution modes") changed when the execution modes are handled,
which affects the result of the floating point constants when the
rounding mode is set in the execution mode. Moved the handling of
the rounding modes before we handle the constants.
v4:
- Rename vtn_decoration "literals" to "operands" (Andres).
- Simplify execution mode parsing util function (Caio).
- Extend the comment about the timing of the handling of the rounding
modes (Caio).
v5:
- Correct extension name (Caio).
- Rename shader info member (Andres).
- Rename float controls enum (Andres).
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Signed-off-by: Andres Gomez <agomez at igalia.com>
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com> [v3]
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=420ad0a1a3d90cf158a4b53c244efb7f4d5610de
Author: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Date: Thu May 31 11:50:54 2018 +0200
spirv: check support for SPV_KHR_float_controls capabilities
v2:
- Correct extension name (Caio).
- Rename supported capabilities member (Andres).
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com> [v1]
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
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