Mesa (master): lima/gpir: Fix 64-bit shift in scheduler spilling

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Module: Mesa
Branch: master
Commit: fed5b605f09ac1a6c23d2aeced7f9abccdf02139
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=fed5b605f09ac1a6c23d2aeced7f9abccdf02139

Author: Connor Abbott <cwabbott0 at gmail.com>
Date:   Thu Sep 19 00:47:28 2019 +0700

lima/gpir: Fix 64-bit shift in scheduler spilling

There are 64 physical registers so the shift must be 64 bits.

Reviewed-by: Vasily Khoruzhick <anarsoul at gmail.com>

---

 src/gallium/drivers/lima/ir/gp/scheduler.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/lima/ir/gp/scheduler.c b/src/gallium/drivers/lima/ir/gp/scheduler.c
index e069079591c..bf8bd63e57c 100644
--- a/src/gallium/drivers/lima/ir/gp/scheduler.c
+++ b/src/gallium/drivers/lima/ir/gp/scheduler.c
@@ -861,12 +861,12 @@ static uint64_t get_available_regs(sched_ctx *ctx, gpir_node *node,
          if (instr->reg0_use_count == 0)
             use_available = ~0ull;
          else if (!instr->reg0_is_attr)
-            use_available = 0xf << (4 * instr->reg0_index);
+            use_available = 0xfull << (4 * instr->reg0_index);
 
          if (instr->reg1_use_count == 0)
             use_available = ~0ull;
          else
-            use_available |= 0xf << (4 * instr->reg1_index);
+            use_available |= 0xfull << (4 * instr->reg1_index);
 
          available &= use_available;
       }