Mesa (master): radv: Fix L2 cache rinse programming.

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Module: Mesa
Branch: master
Commit: c372dc762dac1c0bdf27b5cba112b61c15b8f862
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=c372dc762dac1c0bdf27b5cba112b61c15b8f862

Author: Timur Kristóf <timur.kristof at gmail.com>
Date:   Thu Sep 26 09:37:16 2019 +0200

radv: Fix L2 cache rinse programming.

According to radeonsi, GLM doesn't support WB alone, so
we have to set INV too when WB is set.

Signed-off-by: Timur Kristóf <timur.kristof at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>

---

 src/amd/vulkan/si_cmd_buffer.c | 14 +++++++++-----
 1 file changed, 9 insertions(+), 5 deletions(-)

diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
index 9dd328f968f..3ca66acb364 100644
--- a/src/amd/vulkan/si_cmd_buffer.c
+++ b/src/amd/vulkan/si_cmd_buffer.c
@@ -886,15 +886,19 @@ gfx10_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
 		gcr_cntl |= S_586_GL1_INV(1) | S_586_GLV_INV(1);
 	if (flush_bits & RADV_CMD_FLAG_INV_L2) {
 		/* Writeback and invalidate everything in L2. */
-		gcr_cntl |= S_586_GL2_INV(1) | S_586_GLM_INV(1);
+		gcr_cntl |= S_586_GL2_INV(1) | S_586_GL2_WB(1) |
+		            S_586_GLM_INV(1) | S_586_GLM_WB(1);
 	} else if (flush_bits & RADV_CMD_FLAG_WB_L2) {
-		/* Writeback but do not invalidate. */
-		gcr_cntl |= S_586_GL2_WB(1);
+		/* Writeback but do not invalidate.
+		 * GLM doesn't support WB alone. If WB is set, INV must be set too.
+		 */
+		gcr_cntl |= S_586_GL2_WB(1) |
+		            S_586_GLM_WB(1) | S_586_GLM_INV(1);
 	}
 
 	/* TODO: Implement this new flag for GFX9+.
-	if (flush_bits & RADV_CMD_FLAG_INV_L2_METADATA)
-		gcr_cntl |= S_586_GLM_INV(1);
+	else if (flush_bits & RADV_CMD_FLAG_INV_L2_METADATA)
+		gcr_cntl |= S_586_GLM_INV(1) | S_586_GLM_WB(1);
 	*/
 
 	if (flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB | RADV_CMD_FLAG_FLUSH_AND_INV_DB)) {