Mesa (master): 30 new commits

Mon Sep 30 12:41:27 UTC 2019

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=7be00b2a06d09e8f3cf2257c7449219a4685ed7f
Author: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>
Date:   Sat Sep 28 13:05:12 2019 -0400

    pan/midgard: Allow scheduling conditions with constants
    
    Now that we have constant adjustment logic abstracted, we can do this
    safely. Along with the csel inversion patch, this allows many more
    common csel ops to inline their condition in the bundle.
    
    Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=c20063aa4af5d31ff706bcd4026a5c9fa575dd8b
Author: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>
Date:   Sat Sep 28 12:39:15 2019 -0400

    pan/midgard: Add csel invert optimization
    
    Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=f0f4b3954805b76135fbaeb434b9cad3226e287a
Author: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>
Date:   Sat Sep 28 12:38:51 2019 -0400

    pan/midgard: Add mir_flip helper
    
    Useful for various operations on both commutative and anticommutative
    ops.
    
    Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=10037ce52320df38d1cc652f4d1be78053b11ed8
Author: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>
Date:   Sat Sep 28 12:13:52 2019 -0400

    pan/midgard: Tightly pack 32-bit constants
    
    If we can reuse constant slots from other instructions, we would like to
    do so to include more instructions per bundle.
    
    Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=a3ca283bc171e5d241bbd619dd52773f1d0f892d
Author: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>
Date:   Sat Sep 28 10:43:51 2019 -0400

    pan/midgard: Allow writeout to see into the future
    
    If an instruction could be scheduled to vmul to satisfy the writeout
    conditions, let's do that and save an instruction+cycle per fragment
    shader.
    
    Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=12a70ccd9ec7bd4d28bc66a3646942a1a4e055c2
Author: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>
Date:   Sat Sep 28 10:28:48 2019 -0400

    pan/midgard: Allow 6 instructions per bundle
    
    We never had a scheduler good enough to hit this case before! :)
    
    Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=34ff50cadd8157c5f41db301aa26d42af4c708b2
Author: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>
Date:   Sat Sep 28 10:22:35 2019 -0400

    pan/midgard: Only one conditional per bundle allowed
    
    There's no r32 to save ya after you use up r31 :)
    
    Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=2715bd02ee7e67a28ccf96ed24aeb8182bbef747
Author: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>
Date:   Sat Sep 28 09:48:53 2019 -0400

    pan/midgard: Schedule to smul/sadd
    
    Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=57bac68fffe4d7dcb5cf573ca9ad4cd262d3a5e1
Author: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>
Date:   Sat Sep 28 09:48:43 2019 -0400

    pan/midgard: Extend choose_instruction for scalar units
    
    Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=e9edae3ecb1030f4b9a9e58f7962c5ab4abaf440
Author: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>
Date:   Sat Sep 28 09:48:27 2019 -0400

    pan/midgard: Don't double check SCALAR units
    
    Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=d3b3daa9d3f02f4a4d3db91653b04014b67a3666
Author: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>
Date:   Mon Sep 23 08:00:51 2019 -0400

    pan/midgard: Use new scheduler
    
    We still emit in-order but we switch to using the bundles created from
    the new scheduler, which will allow greater flexibility and room for
    out-of-order optimization.
    
    Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=1409af9fc758b88601ceb02a1abf3cd263a224a2
Author: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>
Date:   Fri Sep 27 20:18:16 2019 -0400

    pan/midgard: Add distance metric to choose_instruction
    
    We require chosen instructions to be "close", to avoid ballooning
    register pressure. This is a kludge that will go away once we have
    proper liveness tracking in the scheduler, but for now it prevents a lot
    of needless spilling.
    
    v2: Lower threshold to 6 (from 8). Schedule is hurt, but a few shaders
    that spilled excessively are fixed.
    
    Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>
    
    Derp

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=e9571b53e1b2d7dfa8cff5281890d6111c28fb74
Author: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>
Date:   Fri Sep 27 08:18:54 2019 -0400

    pan/midgard: Add mir_choose_alu helper
    
    Based on a given unit.
    
    Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=8462e8246720b868ef6f26cd6d8076ca7cfdb485
Author: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>
Date:   Mon Sep 23 15:57:58 2019 -0400

    pan/midgard: Implement load/store pairing
    
    We can bundle two load/store together. This eliminates the need for
    explicit load/store pairing in a prepass, as well.
    
    Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=7cf493241061d2d942a8555ec8cfa08be3254045
Author: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>
Date:   Tue Sep 24 09:06:37 2019 -0400

    pan/midgard: Extend csel_swizzle to branches
    
    Conditions for branches don't have a swizzle explicitly in the emitted
    binary, but they do implicitly get swizzled in whatever instruction
    wrote r31, so we need to handle that.
    
    Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=c9ce5a92a0d9e052ec4fc38e88d9aed81200489a
Author: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>
Date:   Mon Sep 23 15:37:53 2019 -0400

    pan/midgard: Add helpers for scheduling conditionals
    
    Conditional instructions (csel and conditional branches) require their
    condition to be written to a special condition pipeline register (r31.w
    for scalar, r31.xyzw for vector). However, pipeline registers are live
    only for the duration of a single bundle. As such, the logic to schedule
    conditionals correct is surprisingly complex. Essentially, we see if we
    could stuff the conditional within the same bundle as the csel/branch
    without breaking anything; if we can, we do that. If we can't, we add a
    dummy move to make room.
    
    Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=6f92288e85a38ae88e6c73a298891cdde667c8b8
Author: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>
Date:   Fri Sep 27 08:19:51 2019 -0400

    pan/midgard: Implement predicate->unit
    
    This allows ALUs to select for each unit of the bundle separately.
    
    Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=5a9a48b81a2521cef24e016229e3fbbcc00322eb
Author: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>
Date:   Fri Sep 27 15:43:18 2019 -0400

    pan/midgard: Add predicate->exclude
    
    A bit of a kludge but allows setting an implicit dependency of synthetic
    conditional moves on the actual condition, fixing code generated like:
    
       vmul.feq r0, ..
       sadd.imov r31, .., r0
       vadd.fcsel [...]
    
    The imov runs simultaneous with feq so it gets garbage results, but it's
    too late to add an actual dependency practically speaking, since the new
    synthetic imov doesn't have a node associated.
    
    Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=6284f3ec257159aecb9493a71e9d311af3b28b0f
Author: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>
Date:   Mon Sep 23 16:07:53 2019 -0400

    pan/midgard: Add constant intersection filters
    
    In the future, we will want to keep track of which components of
    constants of various sizes correspond to which parts of the bundle
    constants, like in the old scheduler. For now, let's just stub it out
    for a simple rule of one instruction with embedded constants per bundle.
    We can eventually do better, of course.
    
    Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=941bdd208809f67a3c6820b07a71cb0df9f7ff72
Author: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>
Date:   Mon Sep 23 07:51:08 2019 -0400

    pan/midgard: Remove csel constant unit force
    
    Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=da18525b6f563107b2c8899e26690002b144feed
Author: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>
Date:   Sun Sep 22 09:08:33 2019 -0400

    pan/midgard: Add mir_schedule_texture/ldst/alu helpers
    
    We don't actually do any scheduling here yet, but add per-tag helpers to
    consume an instruction, print it, pop it off the worklist.
    
    Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=72a03bcafae8903339329ee74ba4cdd0c75b2814
Author: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>
Date:   Sun Sep 22 09:01:07 2019 -0400

    pan/midgard: Add mir_choose_bundle helper
    
    It's not always obvious what the optimal bundle type should be. Let's
    break out the logic to decide.
    
    Currently set for purely in-order operation.
    
    Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=b5396369d2f4cc4bbff3bd2bf0639257ffb6fde5
Author: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>
Date:   Sun Sep 22 08:50:22 2019 -0400

    pan/midgard: Add mir_update_worklist helper
    
    After we've chosen an instruction, popped it off, and processed it, it's
    time to update the worklist, removing that instruction from the
    dependency graph to allow its dependents to be put onto the worklist.
    
    Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=826fd7308bba1fcd4fd4c94c798f4f45a741e657
Author: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>
Date:   Wed Sep 18 08:26:30 2019 -0400

    pan/midgard: Add mir_choose_instruction stub
    
    In the future, this routine will implement the core scheduling logic to
    decide which instruction out of the worklist will be scheduled next, in
    a way that minimizes cycle count and register pressure.
    
    In the present, we are more interested in replicating in-order
    scheduling with the much-more-powerful out-of-order model. So rather
    than discriminating by a register pressure estimate, we simply choose
    the latest possible instruction in the worklist.
    
    Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=f48038b588df726cd34f5d15e999498310da7432
Author: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>
Date:   Sat Aug 31 11:56:58 2019 -0700

    pan/midgard: Initialize worklist
    
    This flows naturally from the dependency graph
    
    Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=a3b46c0db67360442b648d5fd08e421a97f720f6
Author: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>
Date:   Sat Aug 31 11:55:31 2019 -0700

    pan/midgard: Calculate dependency graph
    
    Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=adda411263217e86345f039aef730665c73732ea
Author: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>
Date:   Sat Aug 31 11:08:39 2019 -0700

    pan/midgard: Add flatten_mir helper
    
    We would like to flatten a linked list of midgard_instructions into an
    array of midgard_instruction pointers on the heap.
    
    Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=0ecfcbf46225bfb14f92a515ca2140ad2cbc4646
Author: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>
Date:   Fri Sep 27 08:20:17 2019 -0400

    pan/midgard: Squeeze indices before scheduling
    
    This allows node_count to be correct while scheduling.
    
    Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=ad05e8a52ce19f5b48302677b0c0f9ec24a27ed8
Author: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>
Date:   Fri Sep 27 17:07:30 2019 -0400

    pan/midgard: Fix component count handling for ldst
    
    It's not based on the writemask and it can't be inferred; it's just
    intrinsic to the op itself.
    
    Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=cc0544a0f564953d454cd41845333122015ecccd
Author: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>
Date:   Fri Sep 27 17:07:10 2019 -0400

    pan/midgard: Add missing parans in SWIZZLE definition
    
    Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>