Mesa (staging/20.0): nir/lower_int64: Lower 8 and 16-bit downcasts with nir_lower_mov64
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Wed Apr 1 16:06:15 UTC 2020
Module: Mesa
Branch: staging/20.0
Commit: 6ddc34f659dd65bd147f31b680ace64cf52808ca
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6ddc34f659dd65bd147f31b680ace64cf52808ca
Author: Jason Ekstrand <jason at jlekstrand.net>
Date: Sat Mar 28 11:22:43 2020 -0500
nir/lower_int64: Lower 8 and 16-bit downcasts with nir_lower_mov64
We have the code to do the lowering, we were just missing the
boilerplate bits to make should_lower_int64_alu_instr return true.
Fixes: 62d55f12818e "nir: Wire up int64 lowering functions"
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4365>
(cherry picked from commit 14a49f31d3977c2b072b9ef2fdeebebca69fe1d7)
---
.pick_status.json | 2 +-
src/compiler/nir/nir_lower_int64.c | 8 ++++++++
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/.pick_status.json b/.pick_status.json
index 1d21cdaf6f3..d2a5fe1200d 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -526,7 +526,7 @@
"description": "nir/lower_int64: Lower 8 and 16-bit downcasts with nir_lower_mov64",
"nominated": true,
"nomination_type": 1,
- "resolution": 0,
+ "resolution": 1,
"master_sha": null,
"because_sha": "62d55f12818e55bdbe83cf164f9af37a1a6d64d8"
},
diff --git a/src/compiler/nir/nir_lower_int64.c b/src/compiler/nir/nir_lower_int64.c
index 6e3f8526f7b..e18a5481225 100644
--- a/src/compiler/nir/nir_lower_int64.c
+++ b/src/compiler/nir/nir_lower_int64.c
@@ -692,8 +692,12 @@ nir_lower_int64_op_to_options_mask(nir_op opcode)
return nir_lower_divmod64;
case nir_op_b2i64:
case nir_op_i2b1:
+ case nir_op_i2i8:
+ case nir_op_i2i16:
case nir_op_i2i32:
case nir_op_i2i64:
+ case nir_op_u2u8:
+ case nir_op_u2u16:
case nir_op_u2u32:
case nir_op_u2u64:
case nir_op_bcsel:
@@ -855,7 +859,11 @@ should_lower_int64_alu_instr(const nir_instr *instr, const void *_options)
switch (alu->op) {
case nir_op_i2b1:
+ case nir_op_i2i8:
+ case nir_op_i2i16:
case nir_op_i2i32:
+ case nir_op_u2u8:
+ case nir_op_u2u16:
case nir_op_u2u32:
assert(alu->src[0].src.is_ssa);
if (alu->src[0].src.ssa->bit_size != 64)
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