Mesa (master): nir: place aligned members after bitfields in shader_info.tess

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Module: Mesa
Branch: master
Commit: c07bbdbe8268a2c80c602f71eb413f0d84920038
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=c07bbdbe8268a2c80c602f71eb413f0d84920038

Author: Mark Janes <markjanes at swizzler.org>
Date:   Tue Mar 31 16:41:28 2020 -0700

nir: place aligned members after bitfields in shader_info.tess

The placement of new shader_info.tess members unnecessarily wastes
space by interspersing 64bit members between bitfields.

Fixes: f1dd81ae104 ("nir: Collect if shader uses cross-invocation or indirect I/O.")
Reviewed-by: Timur Kristóf <timur.kristof at gmail.com>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4408>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4408>

---

 src/compiler/shader_info.h | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/compiler/shader_info.h b/src/compiler/shader_info.h
index 48a32f6f4ff..be3a6a542e8 100644
--- a/src/compiler/shader_info.h
+++ b/src/compiler/shader_info.h
@@ -330,6 +330,10 @@ typedef struct shader_info {
          uint8_t tcs_vertices_out;
          enum gl_tess_spacing spacing:2;
 
+         /** Is the vertex order counterclockwise? */
+         bool ccw:1;
+         bool point_mode:1;
+
          /* Bit mask of TCS per-vertex inputs (VS outputs) that are used
           * with a vertex index that is NOT the invocation id
           */
@@ -339,10 +343,6 @@ typedef struct shader_info {
           * with a vertex index that is NOT the invocation id
           */
          uint64_t tcs_cross_invocation_outputs_read;
-
-         /** Is the vertex order counterclockwise? */
-         bool ccw:1;
-         bool point_mode:1;
       } tess;
    };
 } shader_info;