Mesa (20.0): 68 new commits
GitLab Mirror
gitlab-mirror at kemper.freedesktop.org
Wed Apr 1 21:41:26 UTC 2020
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a68048153260fe33f2ec5df48f772f4d1ceaed03
Author: Eric Engestrom <eric at engestrom.ch>
Date: Wed Apr 1 23:40:37 2020 +0200
docs/relnotes: add sha256sum for 20.0.3
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=103f12d23e70a0944f78c1e758190933cfff0a64
Author: Eric Engestrom <eric at engestrom.ch>
Date: Wed Apr 1 23:25:56 2020 +0200
VERSION: bump to 20.0.3
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b04ae1f964c977035d9c8fd4144424387e0d868e
Author: Eric Engestrom <eric at engestrom.ch>
Date: Wed Apr 1 23:24:57 2020 +0200
docs: add release notes for 20.0.3
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5e85ed86eb72c45741bd3f0ae32c04e8bd54b381
Author: Thomas Hellstrom <thellstrom at vmware.com>
Date: Sat Mar 28 18:02:25 2020 +0100
svga, winsys/svga: Fix persistent memory discard maps
The kernel driver requires immediate notification using a
BindGBSurface command when a graphics coherent memory resource changes
backing MOB, so that it can start dirty-tracking the new MOB.
Since we always use graphics coherent memory for persistent memory, enqueue
and flush a BindGBSurface commmand at map time rather than at unmap time.
Since we're dealing with persistent memory, It's OK to flush while mapped.
This fixes an issue with gnome-shell / Wayland which uses persistent
memory together with discard maps when we advertise ARB_buffer_storage.
XWayland clients will render incorrectly.
Fixes: 71b43490dd ("svga: Support ARB_buffer_storage")
Signed-off-by: Thomas Hellstrom <thellstrom at vmware.com>
Reviewed-by: Neha Bhende <bhenden at vmware.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
Reviewed-by: Reviewed-by: Roland Scheidegger <sroland at vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4399>
(cherry picked from commit 46fdc288fb52345134fd9aacd6d7ff71c7b747bb)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9c8dab082f8564ce643104287a4533a2f470069b
Author: Timothy Arceri <tarceri at itsqueeze.com>
Date: Sat Mar 28 02:17:54 2020 +1100
nir: fix crash in varying packing on interface mismatch
For example when the outputs are scalars but the inputs are struct
members.
Fixes: 26aa460940f6 ("nir: rewrite varying component packing")
Reviewed-By: Timur Kristóf <timur.kristof at gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4351>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4351>
(cherry picked from commit 0f4a81430e65e09db13d2472fd46105a95ea625d)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=84531156eeae2b3c8980322c02babc894d852984
Author: Jason Ekstrand <jason at jlekstrand.net>
Date: Mon Mar 30 11:25:07 2020 -0500
spirv: Implement OpCopyObject and OpCopyLogical as blind copies
Because the types etc. are required to logically match, we can just
copy-propagate the guts of the vtn_value. This was causing issues with
some new CTS tests that are doing an OpCopyObject of a sampler which is
a special-cased type in spirv_to_nir. Of course, this is only a partial
solution. Ideally, we've got a bit of work to do to make all the
composite stuff able to handle all types including images, sampler, and
combined image/samplers but this gets some CTS tests passing.
Cc: mesa-stable at lists.freedesktop.org
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Acked-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4375>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4375>
(cherry picked from commit 7a53e67816ed9baf7d825ed60ee59f0c05f9df48)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=52aafdafb33edd665603bafeea94aa65727b8b55
Author: Eric Engestrom <eric at engestrom.ch>
Date: Wed Apr 1 18:05:22 2020 +0200
.pick_status.json: Update to 70ac7f5b0c46370075a35067c9f7dfe78e84b16d
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e51b749f1dacba70a4bc690246f8484301eb1de8
Author: Jason Ekstrand <jason at jlekstrand.net>
Date: Thu Mar 26 12:22:48 2020 -0500
anv: Account for the header in anv_state_stream_alloc
If we have an allocation that's exactly the block size, we end up
computing a new block size to allocate that's exactly the block size,
add in the header, and then assert fail. When computing the block size,
we need to account for the header.
Fixes: 955127db937 "anv/allocator: Add support for large stream..."
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4336>
(cherry picked from commit 63bec07e14d1cd8e01bf45bcda341bb364620cfc)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6ddc34f659dd65bd147f31b680ace64cf52808ca
Author: Jason Ekstrand <jason at jlekstrand.net>
Date: Sat Mar 28 11:22:43 2020 -0500
nir/lower_int64: Lower 8 and 16-bit downcasts with nir_lower_mov64
We have the code to do the lowering, we were just missing the
boilerplate bits to make should_lower_int64_alu_instr return true.
Fixes: 62d55f12818e "nir: Wire up int64 lowering functions"
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4365>
(cherry picked from commit 14a49f31d3977c2b072b9ef2fdeebebca69fe1d7)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=99471dbddc7644e6368d6fc5cd66b8c750f4ef5f
Author: Rob Clark <robdclark at chromium.org>
Date: Sat Mar 28 11:14:05 2020 -0700
util: fix u_fifo_pop()
Seems like no one ever depended on it to actually return false when fifo
is empty.
Fixes: 6e61d062093 ("util: Add super simple fifo")
Signed-off-by: Rob Clark <robdclark at chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4366>
(cherry picked from commit ffd32266780a83695ae5dd8d36b73fe970cfe4dc)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b571cfabb61ed1a8cdb35373c9ba75d9c48ce3eb
Author: Rhys Perry <pendingchaos02 at gmail.com>
Date: Thu Mar 26 15:50:31 2020 +0000
util/u_queue: fix race in total_jobs_size access
Signed-off-by: Rhys Perry <pendingchaos02 at gmail.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
CC: <mesa-stable at lists.freedesktop.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4335>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4335>
(cherry picked from commit 1ef9658906655edb6b2beaf2951a9dc81d93b827)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1a6ce0f9afe39a6783ca70119479d442bcc6597d
Author: Rhys Perry <pendingchaos02 at gmail.com>
Date: Thu Mar 26 15:49:05 2020 +0000
glsl: fix race in instance getters
Insertions can modify entry->data. Seems to fix random Fossilize crashes.
Signed-off-by: Rhys Perry <pendingchaos02 at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Reviewed-by: Eric Engestrom <eric at engestrom.ch>
Reviewed-by: Eric Anholt <eric at anholt.net>
CC: <mesa-stable at lists.freedesktop.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4335>
(cherry picked from commit d101ca3f5ad85731cedbe7ab399d4323cca1aac6)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b97550253de3fbb85325d9a6162b90735a8b1e46
Author: Eric Engestrom <eric at engestrom.ch>
Date: Tue Mar 31 12:27:49 2020 +0200
.pick_status.json: Update to 5f4d9b419a1c931ad468b8b22b8a95b1216891e4
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f44779d7eb1e19034ef96366b29fe01ec58e514b
Author: Erik Faye-Lund <erik.faye-lund at collabora.com>
Date: Tue Mar 10 18:19:15 2020 +0100
vtn/opencl: fully enable OpenCLstd_Clz
Fixes: 7325f6ac987 ("vtn/opencl: add clz support")
Reviewed-by: Boris Brezillon <boris.brezillon at collabora.com>
Reviewed-by: Karol Herbst <kherbst at redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4318>
(cherry picked from commit 4821ec6d8fcd0287ee9ea5afdd922da5ab787900)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=243cc870322d7b6eb6ee71c2889d8890fd253c7b
Author: Erik Faye-Lund <erik.faye-lund at collabora.com>
Date: Tue Mar 24 10:58:14 2020 +0100
pipebuffer: clean up cast-warnings
This code produces warnings, so let's fix that. The problem is that
casting a pointer to an integer of non-pointer-size triggers warnings on
MSVC, and on 64-bit Windows unsigned long is 32-bit large.
So let's instead use uintptr_t, which is exactly for these kinds of
things.
While we're at it, let's make the resulting index a plain "unsigned",
which is the type this originated from before we started with this
cast-dance.
Fixes: 1a66ead1c75 ("pipebuffer, winsys/svga: Add functionality to update pb_validate_entry flags")
Reviewed-by: Brian Paul <brianp at vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4297>
(cherry picked from commit 079cb4949dd3199ea5693cc0c6ac4c3d838ee022)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3facfb3435dd1264d87741869a9befdb7c991a5e
Author: Rhys Perry <pendingchaos02 at gmail.com>
Date: Fri Mar 20 16:07:08 2020 +0000
aco: implement 64-bit VGPR constant copies in handle_operands()
64-bit VGPR constant copies can happen because of 64-bit constant copy
propagation. Since this optimization is beneficial and more annoying to
deal with in the optimizer, I've implemented 64-bit VGPR constant copies
in handle_operands().
This also sets copy_operation::size correctly for 64-bit constant copies.
Cc: 20.0 <mesa-stable at lists.freedesktop.org>
Signed-off-by: Rhys Perry <pendingchaos02 at gmail.com>
Reviewed-by: Daniel Schürmann <daniel at schuermann.dev>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4260>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4260>
(cherry picked from commit 43918c9a7fc76b56a521d5eea6a8d2b3fb675a15)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1e598bf8e0a1e94fa87235b02c58b93996ea93f4
Author: Timur Kristóf <timur.kristof at gmail.com>
Date: Wed Mar 11 13:39:46 2020 +0100
radv/llvm: fix subgroup shuffle for chips without bpermute
bpermute only exists on GFX8+ and only with Wave32 on GFX10. Instead
we have to use readlane with a waterfall loop to defeat the LLVM
backend.
This fixes DOOM Eternal which requires subgroup shuffle.
Cc: <mesa-stable at lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4284>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4284>
(cherry picked from commit 7ac8bb33cd6025f805a390e7647506e932f4db0d)
Squashed with:
radv: Enable subgroup shuffle on GFX10 when ACO is used.
Signed-off-by: Timur Kristóf <timur.kristof at gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4159>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4159>
(cherry picked from commit cfa299eadb21893348c60906dfde8feb175c7f14)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=db199be2c3ed667310defbe4818a138e671f20ef
Author: Rob Clark <robdclark at chromium.org>
Date: Sun Mar 22 12:37:12 2020 -0700
freedreno/ir3/ra: fix array liveranges
Fixes: 1b658533e11 ("freedreno/ir3: extend liverange of arrays")
Signed-off-by: Rob Clark <robdclark at chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
(cherry picked from commit d2cc92c747c20613190ba330f22f219d26422cfa)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=284f3ce6bc4e6e0868b06441ab7d8ea923bb8217
Author: Timothy Arceri <tarceri at itsqueeze.com>
Date: Thu Mar 26 12:23:23 2020 +1100
nir: fix packing of TCS varyings not read by the TES
Unlike other stages TCS outputs not read by the TES cannot always
be demoted to globals e.g. when they are read by other TCS
invocations.
We were not taking these outputs into account when packing which
could result in other outputs being assigned to the same location.
Here we make sure to gather information on these outputs and group
them together when packing.
This fixes rendering issues in QUBE 2 via Proton.
Closes: #2653
Fixes: 26aa460940f6 ("nir: rewrite varying component packing")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4328>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4328>
(cherry picked from commit b5e00f5c2bd35920a1aaf9bb676c784d5d18b6fd)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c16dfe1c63dcc62c3ae266601bd337b0dc9d5430
Author: Timothy Arceri <tarceri at itsqueeze.com>
Date: Thu Mar 26 19:03:51 2020 +1100
glsl: fix varying packing for 64bit integers
Without this we can incorrectly end up marking things as making
use of ARB_enhanced_layouts style packing.
Cc: 19.3 20.0 <mesa-stable at lists.freedesktop.org>
Reviewed-by: Dave Airlie <airlied at redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4328>
(cherry picked from commit 8b9ebbcb546816f525298dc24711c1922751e312)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=dfc0a5cc14d33ea94555d4f4b316485f23cb1bd1
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Thu Mar 26 11:40:35 2020 +0100
ac/nir: use llvm.amdgcn.rcp in ac_build_fdiv()
Instead of emitting 1.0 / x which includes a slow division that
LLVM doesn't always optimize even if the metadata is correctly set.
No pipeline-db changes with VEGA10/LLVM 9.
pipeline-db (VEGA10/LLVM 10):
Totals from affected shaders:
SGPRS: 6672 -> 6672 (0.00 %)
VGPRS: 6652 -> 6652 (0.00 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Code Size: 561780 -> 561692 (-0.02 %) bytes
Max Waves: 1043 -> 1043 (0.00 %)
pipeline-db (VEGA10/LLVM 11 - 92744f62478):
Totals from affected shaders:
SGPRS: 84608 -> 83768 (-0.99 %)
VGPRS: 106768 -> 106636 (-0.12 %)
Spilled SGPRs: 1625 -> 1713 (5.42 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Code Size: 10850936 -> 10726712 (-1.14 %) bytes
Max Waves: 3152 -> 3180 (0.89 %)
LLVM 11 (master) is more affected than previous versions, but
based on the small impact with LLVM 9/10, I decided to emit it
unconditionally.
Cc: 20.0 <mesa-stable at lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4326>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4326>
(cherry picked from commit ba2ec1f369d2c97fc7c54ecd52b0addcfd349a31)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6e4db7e726c4eb8ba026666af1069ecbe1a07ceb
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Wed Mar 25 18:17:38 2020 +0100
ac/nir: use llvm.amdgcn.rsq for nir_op_frsq
Instead of emitting 1.0 / sqrt(x) which includes a slow division that
LLVM doesn't always optimize even if the metadata is correctly set.
pipeline-db (VEGA10/LLVM 9):
Totals from affected shaders:
SGPRS: 16872 -> 16864 (-0.05 %)
VGPRS: 15320 -> 15464 (0.94 %)
Spilled SGPRs: 2021 -> 2133 (5.54 %)
Code Size: 1915464 -> 1917476 (0.11 %) bytes
Max Waves: 641 -> 639 (-0.31 %)
pipeline-db (VEGA10/LLVM 10):
Totals from affected shaders:
SGPRS: 43936 -> 44120 (0.42 %)
VGPRS: 41776 -> 41972 (0.47 %)
Spilled SGPRs: 875 -> 875 (0.00 %)
Code Size: 4468164 -> 4468120 (-0.00 %) bytes
Max Waves: 2412 -> 2414 (0.08 %)
pipeline-db (VEGA10/LLVM 11 - 92744f62478):
Totals from affected shaders:
SGPRS: 60096 -> 60096 (0.00 %)
VGPRS: 63552 -> 63648 (0.15 %)
Spilled SGPRs: 6135 -> 6117 (-0.29 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Code Size: 6252996 -> 6249772 (-0.05 %) bytes
Max Waves: 2324 -> 2337 (0.56 %)
LLVM 11 (master) is more affected than previous versions, but
based on the small impact with LLVM 9/10, I decided to emit it
unconditionally.
Cc: 20.0 <mesa-stable at lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4326>
(cherry picked from commit d548384fc686f4e9cc9e6551f9a582cc740f3233)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f4179f1b17d2d6f5e5148e01f5094005299065b4
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Wed Mar 25 18:17:06 2020 +0100
ac/nir: use llvm.amdgcn.rcp for nir_op_frcp
Instead of emitting 1.0 / x which includes a slow division that
LLVM doesn't always optimize even if the metadata is correctly set.
pipeline-db (VEG10/LLVM 9):
Totals from affected shaders:
SGPRS: 50384 -> 50312 (-0.14 %)
VGPRS: 42572 -> 42696 (0.29 %)
Spilled SGPRs: 1372 -> 1372 (0.00 %)
Code Size: 5692040 -> 5691428 (-0.01 %) bytes
Max Waves: 3954 -> 3951 (-0.08 %)
pipeline-db (VEG10/LLVM 10):
Totals from affected shaders:
SGPRS: 78512 -> 78464 (-0.06 %)
VGPRS: 62408 -> 62484 (0.12 %)
Spilled SGPRs: 1502 -> 1502 (0.00 %)
Code Size: 8106188 -> 8103372 (-0.03 %) bytes
Max Waves: 7759 -> 7753 (-0.08 %)
pipeline-db (VEGA10/LLVM 11 - 92744f62478):
Totals from affected shaders:
SGPRS: 112760 -> 113232 (0.42 %)
VGPRS: 111132 -> 110568 (-0.51 %)
Spilled SGPRs: 5870 -> 5940 (1.19 %)
Spilled VGPRs: 650 -> 652 (0.31 %)
Code Size: 11887232 -> 11561744 (-2.74 %) bytes
Max Waves: 8964 -> 9015 (0.57 %)
LLVM 11 (master) is more affected than previous versions, but
based on the small impact with LLVM 9/10, I decided to emit it
unconditionally.
Cc: 20.0 <mesa-stable at lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4326>
(cherry picked from commit 66426ce119b3b647f9ace62b74f18342cacd43a4)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=cbc7ba2e473e56b5c02bf422f8a7d51945b0d693
Author: Francisco Jerez <currojerez at riseup.net>
Date: Thu Mar 19 13:08:56 2020 -0700
intel/fs/gen12: Fix interaction of SWSB dependency combination with EU fusion workaround.
This has been reported to fix a hang in Shadow of Mordor on Gen12.
One of its compute shaders seems to cause an in-order exec_all
dependency to be merged into an out-of-order SET dependency slot,
which would prevent us from baking the SET dependency into the parent
instruction, leading to an assert failure in emit_inst_dependencies()
(Thanks to Rafael for noticing that). Prevent that by avoiding
combination of in-order dependencies whenever that would cause a SET
dependency to be demoted to a SYNC.NOP instruction.
Fixes: e14529ff3262a527 "intel/fs/gen12: Workaround data coherency issues due to broken NoMask control flow."
Tested-by: Rafael Antognolli <rafael.antognolli at intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
(cherry picked from commit 36c155a0178d6f05d65a9acfe5b7553d7a522f07)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c0927e9f72d9f543dda71c0b70fda3f8369de084
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Sat Mar 14 08:57:02 2020 +0200
glsl: set error_emitted true if type not ok for assignment
Patch changes also existing assert to not trigger when we have
error types in assignment.
v2: simplify, cleanup (Ian)
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2629
Fixes: d1fa69ed61d ("glsl: do not attempt assignment if operand type not parsed correctly")
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4178>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4178>
(cherry picked from commit 0847fe6e7fa6ee07420c6eed95bfee036748bc6a)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=08a2a2025b3303b0cbacf0fecee355d65a17ac74
Author: Eric Engestrom <eric at engestrom.ch>
Date: Sun Mar 29 23:07:08 2020 +0200
.pick_status.json: Update to 8970b7839aebefa7207c9535ac34ab4e8cc0ae25
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=96868b7297b42eb52b1bf2c0f291e8b1a4176ba5
Author: Marek Vasut <marex at denx.de>
Date: Sun Mar 22 03:48:05 2020 +0100
etnaviv: Emit PE.ALPHA_COLOR_EXT* on GPUs with half-float support
At least GC880 (iMX6S), GC2000 (iMX6Q) blobs do not emit the
PE.ALPHA_COLOR_EXT0 and PE.ALPHA_COLOR_EXT1 into the command
stream. The GCnano (STM32MP1) is not affected by this change
either. This is because neither of these GPUs support the
half-float feature.
Emit PE.ALPHA_COLOR_EXT* in etnaviv only if half-float support
is present in the GPU. This fixes all of the currently failing
dEQPs in this group:
dEQP-GLES2.functional.fragment_ops.blend.*
Fixes: 76adf041f25 ("etnaviv: fix blend color on newer GPUs")
Signed-off-by: Marek Vasut <marex at denx.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner at gmail.com>
Reviewed-by: Jonathan Marek <jonathan at marek.ca>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4277>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4277>
(cherry picked from commit 9e78f17b74a862e34891901cde8292f91adeb655)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2e745e0ed350b55e8e26dc0e9bf4423f0c3c7fda
Author: Erik Faye-Lund <erik.faye-lund at collabora.com>
Date: Tue Mar 24 11:04:39 2020 +0100
rbug: do not return void-value
Returning a void-value is nonsensical, and in this case it seems like a
mistake.
This eliminates a warning when building on MSVC.
Fixes: fb04e5da97d ("gallium: add pipe_screen::finalize_nir")
Reviewed-by: Brian Paul <brianp at vmware.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4297>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4297>
(cherry picked from commit 8c30b9d9878b14098d01a4bae5d51f1392e3baff)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=85c2780f7895c64936efd91126de8e25c91ddce0
Author: Eric Engestrom <eric at engestrom.ch>
Date: Thu Mar 26 13:40:47 2020 +0100
.pick_status.json: Update to 05069e1f0794aadd40ce9269f858e50c64254388
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=64092f4de31c31a41fc4b97808847aa6495e0a1e
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Fri Mar 20 15:10:09 2020 -0700
intel: Add TGL PCI ID
Ref: Bspec 44455
Cc: <mesa-stable at lists.freedesktop.org>
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
(cherry picked from commit f02ae6986740813bf79bde8aad1a0ac5dd7e4d7c)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=fdd4beab686d968a5a787243c9476c0a88405745
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Fri Mar 20 15:08:12 2020 -0700
intel: Update TGL PCI strings
Ref: Bspec 44455
Cc: <mesa-stable at lists.freedesktop.org>
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
(cherry picked from commit 1c6ef0165f03a8e8c20a2c33a78584166a73487c)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ead58ae0c87c8908a6c188b2d2eae47fbd8dca73
Author: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Date: Thu Mar 19 21:30:01 2020 +0200
intel: add new TGL pci ids
Update following kernel : https://patchwork.freedesktop.org/patch/357921/
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Bspec: 44455
Acked-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Scott D Phillips <scott.d.phillips at intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4248>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4248>
(cherry picked from commit 58deebe547014e64d8db3f8cc5e963efe7e0f743)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d41c5951baaa47b67173e3b2e8069d605d2b5392
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Tue Mar 24 15:07:05 2020 +0100
radv: enable VK_KHR_8bit_storage on GFX6-GFX7
Enabling a Vulkan extension doesn't mean that all features need
to be implemented. DOOM Eternal crashes at launch if that ext
is not supported but it doesn't matter if the features are enabled
or not.
Let's enable it like we did for VK_KHR_16bit_storage.
Cc: 19.3 20.0 <mesa-stable at lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4299>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4299>
(cherry picked from commit 238e2ed2100d4d364fefa23bac058100704c0a44)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9cdc30f837c54cbee4a6e92ce624d14dbde78147
Author: Rhys Perry <pendingchaos02 at gmail.com>
Date: Wed Mar 11 20:22:38 2020 +0000
nir/gather_info: fix per-vertex handling in try_mask_partial_io
pipeline-db (Navi, ACO):
Totals from affected shaders:
SGPRS: 6432 -> 6432 (0.00 %)
VGPRS: 11924 -> 11924 (0.00 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Scratch size: 1596 -> 1596 (0.00 %) dwords per thread
Code Size: 575524 -> 518620 (-9.89 %) bytes
LDS: 12187 -> 12187 (0.00 %) blocks
Max Waves: 2695 -> 2695 (0.00 %)
Helps a few hundred Dark Souls 3 shaders.
Signed-off-by: Rhys Perry <pendingchaos02 at gmail.com>
CC: <mesa-stable at lists.freedesktop.org>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4190>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4190>
(cherry picked from commit 9f4ba2d2b4a577a7cf6b38e835f0d1f39965bf08)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c81092f789b0c0f9fe16434b4d8728d2d4dec3d1
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Mar 21 17:54:36 2020 -0400
st/mesa: fix use of uninitialized memory due to st_nir_lower_builtin
reported by valgrind
Cc: 19.3 20.0 <mesa-stable at lists.freedesktop.org>
Reviewed-by: Rob Clark <robdclark at gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4274>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4274>
(cherry picked from commit 719063d4d07a8f2ab2f256ea697083a8eb07e32a)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ca17bf0f812e9bf09dabdada3df7f911c64e7590
Author: Rhys Perry <pendingchaos02 at gmail.com>
Date: Mon Mar 23 13:49:08 2020 +0000
aco: fix boolean undef regclass
Cc: <mesa-stable at lists.freedesktop.org>
Signed-off-by: Rhys Perry <pendingchaos02 at gmail.com>
Reviewed-by: Daniel Schürmann <daniel at schuermann.dev>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4285>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4285>
(cherry picked from commit 17c7f4e30ed8f7a04ae3ad80e39cfbdf8d8ea46c)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c2601fe16b2f23b5cd6b23159d7ff2a3966920b1
Author: Rhys Perry <pendingchaos02 at gmail.com>
Date: Wed Feb 26 13:35:26 2020 +0000
aco: emit IR in IF's merge block instead if the other side ends in a jump
Fixes NIR such as:
if (divergent) {
a = sgpr()
} else {
break;
}
use(a)
Previously we would have emitted:
if (divergent) {
a = sgpr()
}
if (!divergent) {
break;
}
use(a)
But "a" isn't available at it's use. Now we emit:
if (divergent) {
}
if (!divergent) {
break;
}
a = sgpr()
use(a)
pipeline-db (Navi):
Totals from affected shaders:
SGPRS: 1936 -> 1936 (0.00 %)
VGPRS: 1264 -> 1264 (0.00 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 159408 -> 159152 (-0.16 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Max Waves: 81 -> 81 (0.00 %)
Signed-off-by: Rhys Perry <pendingchaos02 at gmail.com>
CC: <mesa-stable at lists.freedesktop.org>
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2557
Reviewed-by: Daniel Schürmann <daniel at schuermann.dev>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3658>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3658>
(cherry picked from commit 9d56ed199b911c1085ea558d243ab543af47ac8e)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f130cbe7168269e0e42bebc240a4ab3567fe630b
Author: Rhys Perry <pendingchaos02 at gmail.com>
Date: Fri Jan 31 16:39:20 2020 +0000
aco: improve check for unreachable loop continue blocks
The old code would have previously caught:
loop {
...
break
}
when it was meant to just catch:
loop {
if (...)
break
else
break
}
Signed-off-by: Rhys Perry <pendingchaos02 at gmail.com>
CC: <mesa-stable at lists.freedesktop.org>
Reviewed-by: Daniel Schürmann <daniel at schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3658>
(cherry picked from commit 8d8c864beba399ae4ee2267f680d1f600ad32767)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a1fd16e507b3381ff97fa74ea60e37a9ead0621d
Author: Rhys Perry <pendingchaos02 at gmail.com>
Date: Fri Jan 31 16:47:10 2020 +0000
aco: skip NIR in unreachable merge blocks
NIR removes most of this but undef instructions for loop header phis can
remain. These were harmless because ACO would DCE them itself.
Signed-off-by: Rhys Perry <pendingchaos02 at gmail.com>
CC: <mesa-stable at lists.freedesktop.org>
Reviewed-by: Daniel Schürmann <daniel at schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3658>
(cherry picked from commit 46e94fd854e8f209ae662826e1794de4c5da2b80)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=275e9392999d7c4fead31285f43758b28df23f2d
Author: Rhys Perry <pendingchaos02 at gmail.com>
Date: Fri Jan 31 12:41:19 2020 +0000
aco: handle missing second predecessors at merge block phis
Signed-off-by: Rhys Perry <pendingchaos02 at gmail.com>
CC: <mesa-stable at lists.freedesktop.org>
Reviewed-by: Daniel Schürmann <daniel at schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3658>
(cherry picked from commit f2c4878de9f2acfd7b23ed2deea1af094b781c7d)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=cb7517be47c27478f5c12180c8ea0e8cf05d5104
Author: Rhys Perry <pendingchaos02 at gmail.com>
Date: Fri Jan 31 12:40:51 2020 +0000
aco: set has_divergent_branch for discards in loops
Signed-off-by: Rhys Perry <pendingchaos02 at gmail.com>
CC: <mesa-stable at lists.freedesktop.org>
Reviewed-by: Daniel Schürmann <daniel at schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3658>
(cherry picked from commit f1a2e1df7882e9d3816f28d6a0827d4ac66ac8f6)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4c2f8b3dd6a2560b6b7b40be685ae728a2c3784f
Author: Marek Olšák <marek.olsak at amd.com>
Date: Fri Mar 20 16:35:45 2020 -0400
ac: fix fast division
This stopped working with LLVM 11 and might occasionally have been broken
on older LLVM, because the metadata was set on the mul, not on the rcp.
Cc: 19.3 20.0 <mesa-stable at lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4268>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4268>
(cherry picked from commit 303842b2dbf30e7dd1a4cd463e76aecf81adebb8)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d48baa3859a45ff8ff493269992b7ee8a3ffcc5a
Author: Neil Armstrong <narmstrong at baylibre.com>
Date: Wed Mar 4 14:39:20 2020 +0100
Revert "ci: Remove T820 from CI temporarily"
This reverts commit 089c8f0b8da86a05bde8359c84085e0b795abf17.
Our office changes are finished and power is now stable in our lab
for T820 CI to run again.
Cc: Daniel Stone <daniels at collabora.com>
Cc: Tomeu Vizoso <tomeu.vizoso at collabora.com>
Signed-off-by: Neil Armstrong <narmstrong at baylibre.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4057>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4057>
(cherry picked from commit 4b61ad372d51681a3fb41b2dc21d2d58eb2becac)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4b5df32e82af0096cf58ffa3a4443c9e540ee6c3
Author: Eric Engestrom <eric at engestrom.ch>
Date: Wed Mar 25 13:59:43 2020 +0100
.pick_status.json: Update to 12711939320e4fcd3a0d86af22da1042ad92035f
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f3766dada2de15dd5be2b56405fa34f5cdf00e91
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Wed Mar 18 18:49:23 2020 +0100
radv: fix optional pSizes parameter when binding streamout buffers
The Vulkan spec 1.2.135 says:
"pSizes is an optional array of buffer sizes, specifying the maximum
number of bytes to capture to the corresponding transform feedback
buffer. If pSizes is NULL, or the value of the pSizes array element
is VK_WHOLE_SIZE, then the maximum bytes captured will be the size
of the corresponding buffer minus the buffer offset."
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2650
Fixes: b4eb029062a ("radv: implement VK_EXT_transform_feedback")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4232>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4232>
(cherry picked from commit 2d3223ca90ae946231c1bfbfd1b450e5e96106a3)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3ab95d1846114c9f56198d734896a3e840affb37
Author: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
Date: Wed Mar 18 17:14:19 2020 -0700
mesa/main: Fix overflow in validation of DispatchComputeGroupSizeARB
An uint64_t can store the result of multiplying two GLuint (uint32_t),
so use that property to check for overflow when calculating the total.
Change the error message so we don't need to care about the actual
total -- which means we don't need a larger than 64-bit value to hold
it.
Fixes: 45ab63c0cb2 ("mesa/main: add support for ARB_compute_variable_groups_size")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4240>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4240>
(cherry picked from commit fdc603292862dd2663b75d18e9abc6096b8020ff)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=52b2c501647f1264cc4d365c5b614a1abdaf88c1
Author: Dylan Baker <dylan at pnwbakers.com>
Date: Fri Mar 20 15:59:40 2020 -0700
.pick_status.json: Update to aee004a7c8900938d1c17f0ac299d40001b383b0
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=57e746cfc04f95d89ad2d8b757eb1d02a44bb264
Author: John Stultz <john.stultz at linaro.org>
Date: Thu Mar 12 21:21:50 2020 +0000
vc4_bufmgr: Remove duplicative VC definition
This is already defined in
src/broadcom/cle/v3d_packet_helpers.h:42:9
And was causing build issues in AOSP when building with mmma
Reviewed-by: Eric Anholt <eric at anholt.net>
Signed-off-by: John Stultz <john.stultz at linaro.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4175>
(cherry picked from commit 0df48e5d1f09c81bdbc9cc501c5a382c9175da33)
Signed-off-by: John Stultz <john.stultz at linaro.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7e7722dca382f68ac6f8d4b66ffbe0782d005694
Author: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Date: Wed Mar 18 20:03:53 2020 +0200
isl: drop min row pitch alignment when set by the driver
When the caller of the isl_surf_init() specifies a row pitch, do not
consider the minimum CCS requirement if it's incompatible with the
caller's value.
isl_surf_get_ccs_surf() will check that the main surface alignment
matches CCS expectations.
v2: Simplify checks (Nanley)
v3: Add Comment about isl_surf_get_ccs_surf() (Jason)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Cc: <mesa-stable at lists.freedesktop.org>
Fixes: a3f6db2c4e92 ("isl: drop CCS row pitch requirement for linear surfaces")
Reviewed-by: Nanley Chery <nanley.g.chery at intel.com>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4243>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4243>
(cherry picked from commit 507abc395940debf59df19d51fdff071cdb9f6ed)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b1cbf7d9faba958dd9fe07f70e23b39210bb3b73
Author: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Date: Thu Feb 20 16:16:33 2020 +0200
isl: only apply main surface ccs pitch constraint with CCS
We could be creating a Y-tiled surface that isn't going to use CCS
(this could be the case when clearly indicated through modifiers).
Don't apply the main surface pitch alignment constraint in that case.
v2: Use logical NOT (Sagar)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Fixes: a3f6db2c4e92 ("isl: drop CCS row pitch requirement for linear surfaces")
Reviewed-by: Nanley Chery <nanley.g.chery at intel.com>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4243>
(cherry picked from commit def3470e9bc1c3c4d93b21cf15b7105e4f553dab)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=18e76206b08eb62ba5e914b6cd44ef3237b0268a
Author: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Date: Tue Oct 15 14:37:45 2019 +0300
isl: properly filter supported display modifiers on Gen9+
Y tiling is supported for display on Gen9+ so don't filter it from the
possible flags.
v2: Drop Yf from display supported tilings on Gen12+ (Jason)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Cc: <mesa-stable at lists.freedesktop.org>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4243>
(cherry picked from commit dab0aadea9494ebf19a0c3e23a38bd01c857b49c)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0414dba695e9297cd3833b45a4e510ff877c934b
Author: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Date: Mon Oct 14 21:26:18 2019 +0300
isl: implement linear tiling row pitch requirement for display
We're missing a requirement for alignment of row pitch for the display
HW. In linear tiling, the row pitch must be a 64bytes aligned.
v2: Use correct formula to align to 64bytes (Chad)
v3: Matching {} (Jason)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Cc: <mesa-stable at lists.freedesktop.org>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4243>
(cherry picked from commit 157a3cf3ecb6917c26508c5bf641e1b8c58e6228)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=29443dad40ad4597a824b69af17c21567e5539bc
Author: Eric Engestrom <eric at engestrom.ch>
Date: Fri Mar 20 00:21:27 2020 +0100
.pick_status.json: Update to 3252041a7872c49e53bb02ffe8b079b5fc43f15e
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4441e00be1a4c75d26d00e119619db7b3757a3f6
Author: Dylan Baker <dylan at pnwbakers.com>
Date: Thu Mar 19 10:01:11 2020 -0700
.pick_status.json: Mark 56de6f698e3f164d97f132203e8159ef0b8e9bb8 as denominated
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=fb341213fabe571a0878f78b1d53dcafd30e2e4f
Author: Rhys Perry <pendingchaos02 at gmail.com>
Date: Fri Mar 13 19:31:03 2020 +0000
nir/gather_info: handle emit_vertex_with_counter
Signed-off-by: Rhys Perry <pendingchaos02 at gmail.com>
Reviewed-By: Timur Kristóf <timur.kristof at gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
CC: <mesa-stable at lists.freedesktop.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4193>
(cherry picked from commit 5193688e1ac696928109ade1b0eb901a91607436)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5e1403722710ec29b0d82bf6e79456cfaea76323
Author: Marek Olšák <marek.olsak at amd.com>
Date: Fri Mar 13 17:54:35 2020 -0400
nir: fix clip/cull_distance_array_size in nir_lower_clip_cull_distance_arrays
This fixes a GPU hang on radeonsi.
It only works if optimizations have already been run.
Cc: 19.3 20.0 <mesa-stable at lists.freedesktop.org>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4194>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4194>
(cherry picked from commit 3c03718fd7813b9023c286101d4f972aa3390de9)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=226ff465b7daa36d63b59686556c2d3c82f687b0
Author: Jason Ekstrand <jason at jlekstrand.net>
Date: Tue Mar 17 13:12:35 2020 -0500
anv: Swizzle fast-clear values
Starting with Gen12, we can fast-clear a lot more surface formats and we
are suddenly in the position of having to fast-clear surfaces with
formats with an implicit swizzle such as VK_FORMAT_R4G4B4A4_UNORM_PACK16
which is represented as ISL_FORMAT_A4B4G4R4 with a BGRA swizzle. In
order for blorp to do the fast-clear color conversion for us, it needs
a properly swizzled color.
This fixes the following Vulkan CTS groups on TGL:
- dEQP-VK.pipeline.blend.format.b4g4r4a4_unorm_pack16.*
- dEQP-VK.api.image_clearing.core.clear_color_image.*.b4g4r4a4*
Cc: mesa-stable at lists.freedesktop.org
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4218>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4218>
(cherry picked from commit 46187bb54fe7a0ccfbafa09c5a168fb45da172d4)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7eb4b33a9af7086701884975927209bfb93636b6
Author: Jason Ekstrand <jason at jlekstrand.net>
Date: Tue Mar 17 13:36:40 2020 -0500
intel/blorp: Add support for swizzling fast-clear colors
Cc: mesa-stable at lists.freedesktop.org
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4218>
(cherry picked from commit 3fb8f1948167c77f05f89b3a0933cbe2a1280b8d)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=12ed35a395a843ce230a84c96efbad7a8d296b1d
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Wed Mar 4 23:00:24 2020 -0800
soft-fp64: Split a block that was missing a cast on a comparison
This function has code like:
if (0x7FD <= zExp) {
if ((0x7FD < zExp) ||
((zExp == 0x7FD) &&
(0x001FFFFFu == zFrac0 && 0xFFFFFFFFu == zFrac1) &&
increment)) {
...
return ...;
}
if (zExp < 0) {
I saw that, and I thought, "Uh... what? Dead code?" I thought it was a
bit fishy, so I grabbed the Berkeley SoftFloat Library 3e code, and
there is similar code in softfloat_roundPackToF64
(source/s_roundPackToF64.c), but it has an extra (uint16_t) cast in the
first comparison. This is basicially a shortcut for
if (zExp < 0 || zExp >= 0x7FD) {
So, having the nesting kind of makes sense. On a CPU, nesting the flow
control can be an optimization. On a GPU, it's just fail. Split the
block so that we don't need the uint16_t cast magic.
Results on the 308 shaders extracted from the fp64 portion of the OpenGL
CTS:
Tiger Lake and Ice Lake had similar results. (Tiger Lake shown)
total instructions in shared programs: 683638 -> 658127 (-3.73%)
instructions in affected programs: 666839 -> 641328 (-3.83%)
helped: 92
HURT: 0
helped stats (abs) min: 26 max: 2456 x̄: 277.29 x̃: 144
helped stats (rel) min: 3.21% max: 4.22% x̄: 3.79% x̃: 3.90%
95% mean confidence interval for instructions value: -345.84 -208.75
95% mean confidence interval for instructions %-change: -3.86% -3.73%
Instructions are helped.
total cycles in shared programs: 5458858 -> 5344600 (-2.09%)
cycles in affected programs: 5360114 -> 5245856 (-2.13%)
helped: 92
HURT: 0
helped stats (abs) min: 126 max: 10300 x̄: 1241.93 x̃: 655
helped stats (rel) min: 1.71% max: 2.37% x̄: 2.12% x̃: 2.17%
95% mean confidence interval for cycles value: -1539.93 -943.94
95% mean confidence interval for cycles %-change: -2.16% -2.08%
Cycles are helped.
Fixes: f111d72596c ("glsl: Add "built-in" functions to do add(fp64, fp64)")
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4142>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4142>
(cherry picked from commit bf2eb3e0eee39e79f5426dfa18d9d3b7f9dfbcb2)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d6b98e432c7d4576a65ef57df85bf7376f8106a0
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Mon Mar 2 18:38:11 2020 -0800
soft-fp64/fsat: Correctly handle NaN
fsat is defined as min(max(a, 0.0), 1.0), and IEEE defines both min and
max to return the non-NaN value when one value is NaN. Based on this,
fsat should definitely return 0.0 for NaN.
Results on the 308 shaders extracted from the fp64 portion of the OpenGL
CTS:
Tiger Lake and Ice Lake had similar results. (Tiger Lake shown)
total instructions in shared programs: 841666 -> 841647 (<.01%)
instructions in affected programs: 122033 -> 122014 (-0.02%)
helped: 7
HURT: 0
helped stats (abs) min: 1 max: 4 x̄: 2.71 x̃: 3
helped stats (rel) min: 0.01% max: 0.02% x̄: 0.02% x̃: 0.01%
95% mean confidence interval for instructions value: -3.74 -1.69
95% mean confidence interval for instructions %-change: -0.02% -0.01%
Instructions are helped.
total cycles in shared programs: 6927246 -> 6926904 (<.01%)
cycles in affected programs: 1038987 -> 1038645 (-0.03%)
helped: 7
HURT: 0
helped stats (abs) min: 18 max: 72 x̄: 48.86 x̃: 54
helped stats (rel) min: 0.03% max: 0.05% x̄: 0.03% x̃: 0.03%
95% mean confidence interval for cycles value: -67.38 -30.33
95% mean confidence interval for cycles %-change: -0.05% -0.02%
Cycles are helped.
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Fixes: a42163cbbc1 ("compiler: Add lowering support for 64-bit saturate operations to software")
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2585
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4142>
(cherry picked from commit 7673dcbd21150e67c5a36bdcc3eee419c025604b)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6923ae24f4cab2786f1f17b0955c8b350293eec5
Author: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
Date: Mon Mar 16 15:10:23 2020 +0100
st/mesa: disallow deferred flush if there are multiple contexts
u_threaded can hang in these situation, with one context waiting on a
deferred fence from the other context.
But the other context isn't flushing its pending work (because it's waiting
for more work to pushed) so everything is stuck.
Fixes: d17b35e671a ("gallium: add PIPE_FLUSH_DEFERRED")
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1430
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4213>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4213>
(cherry picked from commit e7f3a8d6959c74f63c877dd8776fe519d54f946f)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8c9b63ee4082153f497da5f3cfa2b0e5c22dd2ee
Author: Dylan Baker <dylan at pnwbakers.com>
Date: Thu Mar 19 09:51:41 2020 -0700
.pick_status.json: Mark c923de68dd0ab10a5a5fb3196f539707d046d897 as backported
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ee1ebc22aedfead0026ff070928314b4a40b9b96
Author: Dylan Baker <dylan at pnwbakers.com>
Date: Thu Mar 19 09:51:41 2020 -0700
.pick_status.json: Mark 672d10619980687acec329742f055f7f3796c1b8 as backported
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7dc859e2edc6587041d015e4e20858ec4b578451
Author: Dylan Baker <dylan at pnwbakers.com>
Date: Thu Mar 19 09:51:38 2020 -0700
.pick_status.json: Update to cf62c2b2ac69637785f55b790fdd601c17e7e9d5
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2af8aeb9a638f240086cfd40d1df6bfb3eb239ab
Author: Greg V <greg at unrelenting.technology>
Date: Sun Jan 26 14:22:45 2020 +0300
amd/addrlib: fix build on non-x86 platforms
regparm(0) attribute does not work on aarch64 (and presumably powerpc64 and others).
Default to not specifying any calling convention on non-amd64/i386 platforms.
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
(cherry picked from commit 56f31328f207f310ee9b53f3294a23b25b2687e0)
Signed-off-by: John Stultz <john.stultz at linaro.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4239>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4239>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3cabdc38fda398fba8cb2c139a145c27d01a6af4
Author: John Stultz <john.stultz at linaro.org>
Date: Tue Mar 10 03:27:35 2020 +0000
gallium: hud_context: Fix scalar initializer warning.
When trying to build mesa/master under AOSP, I've run into the
following error:
external/mesa3d/src/gallium/auxiliary/hud/hud_context.c:1821:31: error: braces around scalar initializer [-Werror,-Wbraced-scalar-init]
struct sigaction action = {{0}};
^~~
1 error generated.
This patch addresses this by switching to using memset instead of
using an initializer.
Signed-off-by: John Stultz <john.stultz at linaro.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4141>
(cherry picked from commit be22995ecf868a90c6b14fce9b907cf302459e71)
Signed-off-by: John Stultz <john.stultz at linaro.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4239>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=41c56b6cbcc81269af9114ee1b03a585125ddd91
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Mon Mar 16 18:44:18 2020 +0100
radv/gfx10: fix required ballot size with VK_EXT_subgroup_size_control
If compute shaders require a specific subgroup size (ie. Wave32),
we have to use the correct ballot size.
Fixes dEQP-VK.subgroups.ballot_other.compute.*_requiredsubgroupSize.
Fixes: fb07fd4e6cb ("radv: implement VK_EXT_subgroup_size_control")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4230>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4230>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=66c3f0c0631e8a8387a6f4feb672a11cc9310acb
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Mon Mar 16 17:29:33 2020 +0100
radv/gfx10: fix required subgroup size with VK_EXT_subgroup_size_control
If compute shaders require a specific subgroup size (ie. Wave32),
we have to return the correct one.
Fixes dEQP-VK.subgroups.size_control.compute.required_subgroup_size_*.
Fixes: fb07fd4e6cb ("radv: implement VK_EXT_subgroup_size_control")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4230>
More information about the mesa-commit
mailing list