Mesa (master): ac/nir: split 8-bit SSBO stores on GFX6
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Fri Apr 3 08:11:49 UTC 2020
Module: Mesa
Branch: master
Commit: c6bf1597d1e8abf122371118b04a85ee0aa6b3d5
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c6bf1597d1e8abf122371118b04a85ee0aa6b3d5
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Wed Jan 29 14:38:55 2020 +0100
ac/nir: split 8-bit SSBO stores on GFX6
Due to possible alignment issues, make sure to split stores of
8-bit vectors.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4339>
---
src/amd/llvm/ac_nir_to_llvm.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/src/amd/llvm/ac_nir_to_llvm.c b/src/amd/llvm/ac_nir_to_llvm.c
index be1c599fbb1..84067667ef4 100644
--- a/src/amd/llvm/ac_nir_to_llvm.c
+++ b/src/amd/llvm/ac_nir_to_llvm.c
@@ -1740,6 +1740,15 @@ static void visit_store_ssbo(struct ac_nir_context *ctx,
count = 1;
num_bytes = 2;
}
+
+ /* Due to alignment issues, split stores of 8-bit vectors. */
+ if (ctx->ac.chip_class == GFX6 &&
+ elem_size_bytes == 1 && count > 1) {
+ writemask |= ((1u << (count - 1)) - 1u) << (start + 1);
+ count = 1;
+ num_bytes = 1;
+ }
+
data = extract_vector_range(&ctx->ac, base_data, start, count);
offset = LLVMBuildAdd(ctx->ac.builder, base_offset,
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