Mesa (master): radeonsi: don't lower constant arrays to uniforms in GLSL IR

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Module: Mesa
Branch: master
Commit: 1f649ff10764b2f47fd69013f390e9286547cc3b
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=1f649ff10764b2f47fd69013f390e9286547cc3b

Author: Timothy Arceri <tarceri at itsqueeze.com>
Date:   Tue Apr  7 11:28:32 2020 +1000

radeonsi: don't lower constant arrays to uniforms in GLSL IR

This re-enables the change made in 2f5783bc2b82 which was
incorrectly disabled by 3e1dd99adca5.

For radeonsi, we will prefer the NIR pass as it'll generate better code
(some index calculation and a single load vs. a load, then index
calculation, then another load) and oftentimes NIR optimization can kick
in and make all the access indices constant.

Fixes: 3e1dd99adca5 ("radeonsi: Remove a bunch of default handling of pipe caps.")

Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4474>

---

 src/gallium/drivers/radeonsi/si_get.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/gallium/drivers/radeonsi/si_get.c b/src/gallium/drivers/radeonsi/si_get.c
index 2a4a23cec13..4089b944559 100644
--- a/src/gallium/drivers/radeonsi/si_get.c
+++ b/src/gallium/drivers/radeonsi/si_get.c
@@ -218,6 +218,7 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
       return sscreen->info.has_sparse_vm_mappings ? RADEON_SPARSE_PAGE_SIZE : 0;
 
    case PIPE_CAP_UMA:
+   case PIPE_CAP_PREFER_IMM_ARRAYS_AS_CONSTBUF:
       return 0;
 
    case PIPE_CAP_FENCE_SIGNAL: