Mesa (master): freedreno/a6xx: Add registers for the bindless model
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Thu Apr 9 16:15:24 UTC 2020
Module: Mesa
Branch: master
Commit: 122a900d7de826dcd1056f2ad2ea4c72d9129c06
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=122a900d7de826dcd1056f2ad2ea4c72d9129c06
Author: Connor Abbott <cwabbott0 at gmail.com>
Date: Fri Mar 6 11:29:54 2020 +0100
freedreno/a6xx: Add registers for the bindless model
In Vulkan, descriptors for samplers, SSBO's, etc. are collected into
descriptor sets, and shaders can use multiple descriptor sets. At
command-recording time, users can swap out only some of the descriptor
sets, and the driver is supposed to do the minimum amount necessary to
update any internal binding tables, knowing that only some of the
descriptors have changed.
With the old binding model, focused on GL, where there are separate
tables for each type of resource, we can do somewhat better than now by
preserving descriptors from lower descriptor sets when switching higher
descriptor sets. However we still have to copy around descriptors before
each draw.
At least for a6xx, qualcomm went further, essentially copying the Vulkan
binding model as an alternate way to load resources. There's an array of
registers (actually an array for compute and one for everything else),
where each register holds a pointer to a descriptor set that can contain
various different descriptor types. The descriptors are padded out to 16
dwords, so that every instruction can use an index instead of a dword
offset. It's called "bindless", I think, because it can also be used to
implement the old GL bindless extensions (presumably it allows more
samplers and textures than the old model).
This commit adds the register and cmdstream parts. Next up will be the
instruction encoding.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4358>
---
src/freedreno/registers/a6xx.xml | 38 ++++++++++++++++++++++++++++++++++
src/freedreno/registers/adreno_pm4.xml | 1 +
2 files changed, 39 insertions(+)
diff --git a/src/freedreno/registers/a6xx.xml b/src/freedreno/registers/a6xx.xml
index 522f067a11d..ad60d5ddfbf 100644
--- a/src/freedreno/registers/a6xx.xml
+++ b/src/freedreno/registers/a6xx.xml
@@ -2788,6 +2788,15 @@ to upconvert to 32b float internally?
</bitset>
<bitset name="a6xx_sp_xs_config" inline="yes">
+ <!--
+ Each of these are set if the given resource type is used
+ with the Vulkan/bindless binding model.
+ -->
+ <bitfield name="BINDLESS_TEX" pos="0" type="boolean"/>
+ <bitfield name="BINDLESS_SAMP" pos="1" type="boolean"/>
+ <bitfield name="BINDLESS_IBO" pos="2" type="boolean"/>
+ <bitfield name="BINDLESS_UBO" pos="3" type="boolean"/>
+
<bitfield name="ENABLED" pos="8" type="boolean"/>
<!--
number of textures and samplers.. these might be swapped, with GL I
@@ -2995,11 +3004,22 @@ to upconvert to 32b float internally?
<!--
CMD seems always 0x4?? 3d, textureProj, textureLod seem to
skip pre-fetch.. TODO test texelFetch
+ CMD is 0x6 when the Vulkan mode is enabled, and
+ TEX_ID/SAMP_ID refer to the descriptor sets while the
+ indices come from SP_FS_BINDLESS_PREFETCH[n]
-->
<bitfield name="CMD" low="27" high="31"/>
</reg32>
</array>
+ <!-- TODO confirm that this is actually an array -->
+ <array offset="0xa9a3" name="SP_FS_BINDLESS_PREFETCH" stride="1" length="4">
+ <reg32 offset="0" name="CMD">
+ <bitfield name="SAMP_ID" low="0" high="7" type="uint"/>
+ <bitfield name="TEX_ID" low="16" high="23" type="uint"/>
+ </reg32>
+ </array>
+
<reg32 offset="0xa9a7" name="SP_FS_TEX_COUNT" type="uint"/>
<!-- always 0x0 ? -->
@@ -3022,6 +3042,10 @@ to upconvert to 32b float internally?
<reg32 offset="0xa9e6" name="SP_CS_TEX_CONST_LO"/>
<reg32 offset="0xa9e7" name="SP_CS_TEX_CONST_HI"/>
+ <array offset="0xa9e8" name="SP_CS_BINDLESS_BASE" stride="2" length="5">
+ <reg64 offset="0" name="ADDR" type="waddress"/>
+ </array>
+
<array offset="0xa98e" name="SP_FS_OUTPUT" stride="1" length="8">
<doc>per MRT</doc>
<reg32 offset="0x0" name="REG">
@@ -3049,6 +3073,10 @@ to upconvert to 32b float internally?
<reg32 offset="0xab04" name="SP_FS_CONFIG" type="a6xx_sp_xs_config"/>
<reg32 offset="0xab05" name="SP_FS_INSTRLEN" type="uint"/>
+ <array offset="0xab10" name="SP_BINDLESS_BASE" stride="2" length="5">
+ <reg64 offset="0" name="ADDR" type="waddress"/>
+ </array>
+
<!--
Combined IBO state for 3d pipe, used for Image and SSBO write/atomic
instructions VS/HS/DS/GS/FS. See SP_CS_IBO_* for compute shaders.
@@ -3220,6 +3248,11 @@ to upconvert to 32b float internally?
<reg32 offset="0xb99a" name="HLSQ_CS_KERNEL_GROUP_Y"/>
<reg32 offset="0xb99b" name="HLSQ_CS_KERNEL_GROUP_Z"/>
+ <!-- mirror of SP_CS_BINDLESS_BASE -->
+ <array offset="0xb9c0" name="HLSQ_CS_BINDLESS_BASE" stride="2" length="5">
+ <reg64 offset="0" name="ADDR" type="waddress"/>
+ </array>
+
<!-- probably: -->
<reg32 offset="0xbb08" name="HLSQ_UPDATE_CNTL"/>
@@ -3228,6 +3261,11 @@ to upconvert to 32b float internally?
<!-- always 0x0 ? -->
<reg32 offset="0xbb11" name="HLSQ_UNKNOWN_BB11"/>
+ <!-- mirror of SP_BINDLESS_BASE -->
+ <array offset="0xbb20" name="HLSQ_BINDLESS_BASE" stride="2" length="5">
+ <reg64 offset="0" name="ADDR" type="waddress"/>
+ </array>
+
<!-- always 0x80 ? -->
<reg32 offset="0xbe00" name="HLSQ_UNKNOWN_BE00"/>
<!-- always 0x0 ? -->
diff --git a/src/freedreno/registers/adreno_pm4.xml b/src/freedreno/registers/adreno_pm4.xml
index c5d83d06550..23800f781da 100644
--- a/src/freedreno/registers/adreno_pm4.xml
+++ b/src/freedreno/registers/adreno_pm4.xml
@@ -607,6 +607,7 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords)
</enum>
<enum name="a6xx_state_src">
<value name="SS6_DIRECT" value="0"/>
+ <value name="SS6_BINDLESS" value="1"/> <!-- TODO does this exist on a4xx/a5xx? -->
<value name="SS6_INDIRECT" value="2"/>
</enum>
<reg32 offset="0" name="0">
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