Mesa (master): freedreno/ir3/ra: handle array case for SFU select_reg opt

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Module: Mesa
Branch: master
Commit: 96ff2a4099d0eb5c29255429a0e5284e461ec8d5
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=96ff2a4099d0eb5c29255429a0e5284e461ec8d5

Author: Rob Clark <robdclark at chromium.org>
Date:   Fri Apr  3 17:42:05 2020 -0700

freedreno/ir3/ra: handle array case for SFU select_reg opt

The src of the SFU instruction could also be array/reg (non-SSA).
Handle this case too.

The postsched cp pass makes this scenario more likely.

Fixes: cc82521de4e ("freedreno/ir3: round-robin RA")
Signed-off-by: Rob Clark <robdclark at chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4440>

---

 src/freedreno/ir3/ir3_ra.c | 13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/src/freedreno/ir3/ir3_ra.c b/src/freedreno/ir3/ir3_ra.c
index aa200a00620..72682dc6988 100644
--- a/src/freedreno/ir3/ir3_ra.c
+++ b/src/freedreno/ir3/ir3_ra.c
@@ -478,9 +478,16 @@ ra_select_reg_merged(unsigned int n, BITSET_WORD *regs, void *data)
 	 * for write after read hazards:
 	 */
 	struct ir3_instruction *instr = name_to_instr(ctx, n);
-	if (is_sfu(instr) && instr->regs[1]->instr) {
-		struct ir3_instruction *src = instr->regs[1]->instr;
-		unsigned src_n = scalar_name(ctx, src, 0);
+	if (is_sfu(instr)) {
+		struct ir3_register *src = instr->regs[1];
+		int src_n;
+
+		if ((src->flags & IR3_REG_ARRAY) && !(src->flags & IR3_REG_RELATIV)) {
+			struct ir3_array *arr = ir3_lookup_array(ctx->ir, src->array.id);
+			src_n = arr->base + src->array.offset;
+		} else {
+			src_n = scalar_name(ctx, src->instr, 0);
+		}
 
 		unsigned reg = ra_get_node_reg(ctx->g, src_n);