Mesa (master): freedreno/turnip: Update GRAS_LAYER_CNTL to GRAS_MAX_LAYER_INDEX

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Module: Mesa
Branch: master
Commit: 13ce637f1b28381e72470763ff5e39dd3c562476
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=13ce637f1b28381e72470763ff5e39dd3c562476

Author: Brian Ho <brian at brkho.com>
Date:   Mon Apr 13 15:30:31 2020 -0700

freedreno/turnip: Update GRAS_LAYER_CNTL to GRAS_MAX_LAYER_INDEX

After some experimentation, I believe that GRAS_LAYER_CNTL is
actually just a count register storing the number of layers in the
render target. While debugging cube_array geometry tests, I noticed
that the blob was setting an unknown 0x8 to LAYER_CNTL, so I checked
the value of LAYER_CNTL for various layer sizes:

1: LAYER_CNTL=0
2: LAYER_CNTL=1
3: LAYER_CNTL=2
4: LAYER_CNTL=3
9: LAYER_CNTL=8
256: LAYER_CNTL=255
2000: LAYER_CNTL=1999

Seems like this register just stores a count of the largest layer
that can be written to via gl_Layer. This commit updates the reg
docs, freedreno's gs implementation, and turnip's gs implementation.

Fixes dEQP-VK.geometry.layered.cube_array.*

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4541>

---

 src/freedreno/registers/a6xx.xml              |  6 ++----
 src/freedreno/vulkan/tu_cmd_buffer.c          |  5 +----
 src/gallium/drivers/freedreno/a6xx/fd6_gmem.c | 18 +++---------------
 3 files changed, 6 insertions(+), 23 deletions(-)

diff --git a/src/freedreno/registers/a6xx.xml b/src/freedreno/registers/a6xx.xml
index ad60d5ddfbf..96641adbcdb 100644
--- a/src/freedreno/registers/a6xx.xml
+++ b/src/freedreno/registers/a6xx.xml
@@ -1848,10 +1848,8 @@ to upconvert to 32b float internally?
 	  <value value="0x3" name="LAYER_2D_ARRAY"/>
 	</enum>
 
-	<reg32 offset="0x8004" name="GRAS_LAYER_CNTL">
-		<bitfield name="LAYERED" pos="0" type="boolean"/>
-		<bitfield name="TYPE" low="1" high="2" type="a6xx_layer_type"/>
-	</reg32>
+	<!-- index of highest layer that can be written to via gl_Layer -->
+	<reg32 offset="0x8004" name="GRAS_MAX_LAYER_INDEX" type="uint"/>
 
 	<reg32 offset="0x8005" name="GRAS_CNTL">
 		<!-- see also RB_RENDER_CONTROL0 -->
diff --git a/src/freedreno/vulkan/tu_cmd_buffer.c b/src/freedreno/vulkan/tu_cmd_buffer.c
index 557fc857e27..454613c9ea0 100644
--- a/src/freedreno/vulkan/tu_cmd_buffer.c
+++ b/src/freedreno/vulkan/tu_cmd_buffer.c
@@ -489,10 +489,7 @@ tu6_emit_mrt(struct tu_cmd_buffer *cmd,
                       .rt6 = mrt_comp[6],
                       .rt7 = mrt_comp[7]));
 
-   // XXX: We probably can't hardcode LAYER_CNTL_TYPE.
-   tu_cs_emit_regs(cs,
-                   A6XX_GRAS_LAYER_CNTL(.layered = fb->layers > 1,
-                                        .type = LAYER_2D_ARRAY));
+   tu_cs_emit_regs(cs, A6XX_GRAS_MAX_LAYER_INDEX(fb->layers - 1));
 }
 
 void
diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c b/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c
index 7722be8d265..f56b3422d55 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c
@@ -77,8 +77,7 @@ emit_mrt(struct fd_ringbuffer *ring, struct pipe_framebuffer_state *pfb,
 	unsigned srgb_cntl = 0;
 	unsigned i;
 
-	bool layered = false;
-	unsigned type = 0;
+	unsigned max_layer_index = 0;
 
 	for (i = 0; i < pfb->nr_cbufs; i++) {
 		enum a6xx_format format = 0;
@@ -117,18 +116,7 @@ emit_mrt(struct fd_ringbuffer *ring, struct pipe_framebuffer_state *pfb,
 		swap = fd6_resource_swap(rsc, pformat);
 
 		tile_mode = fd_resource_tile_mode(psurf->texture, psurf->u.tex.level);
-
-		if (psurf->u.tex.first_layer < psurf->u.tex.last_layer) {
-			layered = true;
-			if (psurf->texture->target == PIPE_TEXTURE_2D_ARRAY && psurf->texture->nr_samples > 0)
-				type = LAYER_MULTISAMPLE_ARRAY;
-			else if (psurf->texture->target == PIPE_TEXTURE_2D_ARRAY)
-				type = LAYER_2D_ARRAY;
-			else if (psurf->texture->target == PIPE_TEXTURE_CUBE)
-				type = LAYER_CUBEMAP;
-			else if (psurf->texture->target == PIPE_TEXTURE_3D)
-				type = LAYER_3D;
-		}
+		max_layer_index = psurf->u.tex.last_layer - psurf->u.tex.first_layer;
 
 		debug_assert((offset + slice->size0) <= fd_bo_size(rsc->bo));
 
@@ -174,7 +162,7 @@ emit_mrt(struct fd_ringbuffer *ring, struct pipe_framebuffer_state *pfb,
 		.rt6 = mrt_comp[6],
 		.rt7 = mrt_comp[7]));
 
-	OUT_REG(ring, A6XX_GRAS_LAYER_CNTL(.layered = layered, .type = type));
+	OUT_REG(ring, A6XX_GRAS_MAX_LAYER_INDEX(max_layer_index));
 }
 
 static void