Mesa (staging/20.0): iris: drop cache coherent cpu mapping for external BO

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Module: Mesa
Branch: staging/20.0
Commit: 8e81105741cd15d9c5a62899564e346236cb6b3a
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=8e81105741cd15d9c5a62899564e346236cb6b3a

Author: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Date:   Mon Apr 13 18:14:24 2020 +0300

iris: drop cache coherent cpu mapping for external BO

We have to assume any external buffer could be used by the display HW.
In the case that buffer is also CPU mapped, we want to assume no cache
coherency as it is only available between GT & CPU, not display.

Many thanks to Michel Dänzer for the hint!

v2: Move cache coherent drop to bufmgr (Chris)

v3: Also make BO external if created with PIPE_BIND_SHARED (Eric)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Cc: <mesa-stable at lists.freedesktop.org>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2552
Reviewed-by: Eric Anholt <eric at anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4533>
(cherry picked from commit 8ce46f352e9e2ad103a5058895f3ab4ee164ea33)

---

 .pick_status.json                        | 2 +-
 src/gallium/drivers/iris/iris_bufmgr.c   | 7 ++++++-
 src/gallium/drivers/iris/iris_bufmgr.h   | 7 +++++++
 src/gallium/drivers/iris/iris_resource.c | 6 ++++++
 4 files changed, 20 insertions(+), 2 deletions(-)

diff --git a/.pick_status.json b/.pick_status.json
index dc12bd777cd..fe5938d2d2e 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -148,7 +148,7 @@
         "description": "iris: drop cache coherent cpu mapping for external BO",
         "nominated": true,
         "nomination_type": 0,
-        "resolution": 0,
+        "resolution": 1,
         "master_sha": null,
         "because_sha": null
     },
diff --git a/src/gallium/drivers/iris/iris_bufmgr.c b/src/gallium/drivers/iris/iris_bufmgr.c
index ca8db31aed3..c333f7bdaee 100644
--- a/src/gallium/drivers/iris/iris_bufmgr.c
+++ b/src/gallium/drivers/iris/iris_bufmgr.c
@@ -1376,12 +1376,17 @@ iris_bo_make_external_locked(struct iris_bo *bo)
 {
    if (!bo->external) {
       _mesa_hash_table_insert(bo->bufmgr->handle_table, &bo->gem_handle, bo);
+      /* If a BO is going to be used externally, it could be sent to the
+       * display HW. So make sure our CPU mappings don't assume cache
+       * coherency since display is outside that cache.
+       */
+      bo->cache_coherent = false;
       bo->external = true;
       bo->reusable = false;
    }
 }
 
-static void
+void
 iris_bo_make_external(struct iris_bo *bo)
 {
    struct iris_bufmgr *bufmgr = bo->bufmgr;
diff --git a/src/gallium/drivers/iris/iris_bufmgr.h b/src/gallium/drivers/iris/iris_bufmgr.h
index 6bbf691ec51..4aa19350f11 100644
--- a/src/gallium/drivers/iris/iris_bufmgr.h
+++ b/src/gallium/drivers/iris/iris_bufmgr.h
@@ -309,6 +309,13 @@ int iris_bo_get_tiling(struct iris_bo *bo, uint32_t *tiling_mode,
  */
 int iris_bo_flink(struct iris_bo *bo, uint32_t *name);
 
+/**
+ * Make a BO externally accessible.
+ *
+ * \param bo Buffer to make external
+ */
+void iris_bo_make_external(struct iris_bo *bo);
+
 /**
  * Returns 1 if mapping the buffer for write could cause the process
  * to block, due to the object being active in the GPU.
diff --git a/src/gallium/drivers/iris/iris_resource.c b/src/gallium/drivers/iris/iris_resource.c
index e7eaa07b3a2..b752d4cf86b 100644
--- a/src/gallium/drivers/iris/iris_resource.c
+++ b/src/gallium/drivers/iris/iris_resource.c
@@ -774,6 +774,9 @@ iris_resource_create_for_buffer(struct pipe_screen *pscreen,
       return NULL;
    }
 
+   if (templ->bind & PIPE_BIND_SHARED)
+      iris_bo_make_external(res->bo);
+
    return &res->base;
 }
 
@@ -897,6 +900,9 @@ iris_resource_create_with_modifiers(struct pipe_screen *pscreen,
       map_aux_addresses(screen, res);
    }
 
+   if (templ->bind & PIPE_BIND_SHARED)
+      iris_bo_make_external(res->bo);
+
    return &res->base;
 
 fail: