Mesa (master): aco: implement nir_op_f2i8/nir_op_f2u8

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Module: Mesa
Branch: master
Commit: 91aa596ca7ef3411264181f49f58743f5c965710
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=91aa596ca7ef3411264181f49f58743f5c965710

Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date:   Tue Apr 14 16:59:20 2020 +0200

aco: implement nir_op_f2i8/nir_op_f2u8

I think we should really refactor the conversions path.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Daniel Schürmann <daniel at schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4551>

---

 src/amd/compiler/aco_instruction_selection.cpp | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp
index 2acb4e822a3..c0977f518b8 100644
--- a/src/amd/compiler/aco_instruction_selection.cpp
+++ b/src/amd/compiler/aco_instruction_selection.cpp
@@ -2262,6 +2262,7 @@ void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr)
       }
       break;
    }
+   case nir_op_f2i8:
    case nir_op_f2i16: {
       Temp src = get_alu_src(ctx, instr->src[0]);
       if (instr->src[0].src.ssa->bit_size == 16)
@@ -2272,11 +2273,12 @@ void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr)
          src = bld.vop1(aco_opcode::v_cvt_i32_f64, bld.def(v1), src);
 
       if (dst.type() == RegType::vgpr)
-         bld.pseudo(aco_opcode::p_split_vector, Definition(dst), bld.def(v2b), src);
+         bld.pseudo(aco_opcode::p_extract_vector, Definition(dst), src, Operand(0u));
       else
          bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), src);
       break;
    }
+   case nir_op_f2u8:
    case nir_op_f2u16: {
       Temp src = get_alu_src(ctx, instr->src[0]);
       if (instr->src[0].src.ssa->bit_size == 16)
@@ -2287,7 +2289,7 @@ void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr)
          src = bld.vop1(aco_opcode::v_cvt_u32_f64, bld.def(v1), src);
 
       if (dst.type() == RegType::vgpr)
-         bld.pseudo(aco_opcode::p_split_vector, Definition(dst), bld.def(v2b), src);
+         bld.pseudo(aco_opcode::p_extract_vector, Definition(dst), src, Operand(0u));
       else
          bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), src);
       break;