Mesa (master): aco: add and use RegClass::get() helper

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Module: Mesa
Branch: master
Commit: b77d638e1bacfdaffd010b72264ab4c0a5745e73
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=b77d638e1bacfdaffd010b72264ab4c0a5745e73

Author: Rhys Perry <pendingchaos02 at gmail.com>
Date:   Tue Apr 14 20:32:39 2020 +0100

aco: add and use RegClass::get() helper

Eventually, we'll probably want to replace the current
RegClass(type, size) constructor with this.

This has a functional change in that get_reg_class() now creates v1/v2
instead of v4b/v8b.

Signed-off-by: Rhys Perry <pendingchaos02 at gmail.com>
Reviewed-by: Daniel Schürmann <daniel at schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4639>

---

 src/amd/compiler/aco_instruction_selection_setup.cpp | 17 +++--------------
 src/amd/compiler/aco_ir.h                            |  9 +++++++++
 2 files changed, 12 insertions(+), 14 deletions(-)

diff --git a/src/amd/compiler/aco_instruction_selection_setup.cpp b/src/amd/compiler/aco_instruction_selection_setup.cpp
index 7d404b42568..08f8782e8fa 100644
--- a/src/amd/compiler/aco_instruction_selection_setup.cpp
+++ b/src/amd/compiler/aco_instruction_selection_setup.cpp
@@ -226,21 +226,10 @@ sanitize_cf_list(nir_function_impl *impl, bool *divergent, struct exec_list *cf_
 
 RegClass get_reg_class(isel_context *ctx, RegType type, unsigned components, unsigned bitsize)
 {
-   switch (bitsize) {
-   case 1:
+   if (bitsize == 1)
       return RegClass(RegType::sgpr, ctx->program->lane_mask.size() * components);
-   case 8:
-      return type == RegType::sgpr ? s1 : RegClass(type, components).as_subdword();
-   case 16:
-      return type == RegType::sgpr ? RegClass(type, DIV_ROUND_UP(components, 2)) :
-                                     RegClass(type, 2 * components).as_subdword();
-   case 32:
-      return RegClass(type, components);
-   case 64:
-      return RegClass(type, components * 2);
-   default:
-      unreachable("Unsupported bit size");
-   }
+   else
+      return RegClass::get(type, components * bitsize / 8u);
 }
 
 void init_context(isel_context *ctx, nir_shader *shader)
diff --git a/src/amd/compiler/aco_ir.h b/src/amd/compiler/aco_ir.h
index 812a116eb29..d63526e90f3 100644
--- a/src/amd/compiler/aco_ir.h
+++ b/src/amd/compiler/aco_ir.h
@@ -230,6 +230,15 @@ struct RegClass {
    constexpr RegClass as_linear() const { return RegClass((RC) (rc | (1 << 6))); }
    constexpr RegClass as_subdword() const { return RegClass((RC) (rc | 1 << 7)); }
 
+   static constexpr RegClass get(RegType type, unsigned bytes) {
+      if (type == RegType::sgpr) {
+         return RegClass(type, DIV_ROUND_UP(bytes, 4u));
+      } else {
+         return bytes % 4u ? RegClass(type, bytes).as_subdword() :
+                             RegClass(type, bytes / 4u);
+      }
+   }
+
 private:
    RC rc;
 };