Mesa (master): intel/fs: Allow FS_OPCODE_SCHEDULING_FENCE stall on registers
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Wed Apr 29 07:27:15 UTC 2020
Module: Mesa
Branch: master
Commit: 0e96b0d6dd99e80c1ccbc13629ad22a946a74828
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0e96b0d6dd99e80c1ccbc13629ad22a946a74828
Author: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
Date: Fri Jan 17 14:52:13 2020 -0800
intel/fs: Allow FS_OPCODE_SCHEDULING_FENCE stall on registers
It will generate the MOVs (or SYNC_NOP in Gen12+) needed for stall.
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3278>
---
src/intel/compiler/brw_eu_defines.h | 3 +++
src/intel/compiler/brw_fs_generator.cpp | 29 +++++++++++++++++++++++++++--
2 files changed, 30 insertions(+), 2 deletions(-)
diff --git a/src/intel/compiler/brw_eu_defines.h b/src/intel/compiler/brw_eu_defines.h
index d27205d366b..146d3b3f067 100644
--- a/src/intel/compiler/brw_eu_defines.h
+++ b/src/intel/compiler/brw_eu_defines.h
@@ -465,6 +465,9 @@ enum opcode {
/**
* Scheduling-only fence.
+ *
+ * Sources can be used to force a stall until the registers in those are
+ * available. This might generate MOVs or SYNC_NOPs (Gen12+).
*/
FS_OPCODE_SCHEDULING_FENCE,
diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp
index fa2abd48553..b055110ddf8 100644
--- a/src/intel/compiler/brw_fs_generator.cpp
+++ b/src/intel/compiler/brw_fs_generator.cpp
@@ -2228,8 +2228,33 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
}
case FS_OPCODE_SCHEDULING_FENCE:
- if (unlikely(debug_flag))
- disasm_info->use_tail = true;
+ if (inst->sources == 0 && inst->sched.regdist == 0 &&
+ inst->sched.mode == TGL_SBID_NULL) {
+ if (unlikely(debug_flag))
+ disasm_info->use_tail = true;
+ break;
+ }
+
+ if (devinfo->gen >= 12) {
+ /* Use the available SWSB information to stall. A single SYNC is
+ * sufficient since if there were multiple dependencies, the
+ * scoreboard algorithm already injected other SYNCs before this
+ * instruction.
+ */
+ brw_SYNC(p, TGL_SYNC_NOP);
+ } else {
+ for (unsigned i = 0; i < inst->sources; i++) {
+ /* Emit a MOV to force a stall until the instruction producing the
+ * registers finishes.
+ */
+ brw_MOV(p, retype(brw_null_reg(), BRW_REGISTER_TYPE_UW),
+ retype(src[i], BRW_REGISTER_TYPE_UW));
+ }
+
+ if (inst->sources > 1)
+ multiple_instructions_emitted = true;
+ }
+
break;
case SHADER_OPCODE_INTERLOCK:
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