Mesa (master): ac/surface: rename micro tile mode enums like gfx10 uses them
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Wed Apr 29 15:03:24 UTC 2020
Module: Mesa
Branch: master
Commit: 25d3cc293e9e4b21a965fe086537a4b448424bd8
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=25d3cc293e9e4b21a965fe086537a4b448424bd8
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Apr 23 00:31:36 2020 -0400
ac/surface: rename micro tile mode enums like gfx10 uses them
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4697>
---
src/amd/common/ac_surface.c | 12 ++++++------
src/amd/common/ac_surface.h | 8 +++++---
src/gallium/drivers/radeonsi/si_clear.c | 10 +++++-----
src/gallium/winsys/radeon/drm/radeon_drm_surface.c | 2 +-
4 files changed, 17 insertions(+), 15 deletions(-)
diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index 67abb7871d5..55595a66781 100644
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -952,14 +952,14 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
surf->is_linear = surf->u.legacy.level[0].mode == RADEON_SURF_MODE_LINEAR_ALIGNED;
surf->is_displayable = surf->is_linear ||
surf->micro_tile_mode == RADEON_MICRO_MODE_DISPLAY ||
- surf->micro_tile_mode == RADEON_MICRO_MODE_ROTATED;
+ surf->micro_tile_mode == RADEON_MICRO_MODE_RENDER;
/* The rotated micro tile mode doesn't work if both CMASK and RB+ are
* used at the same time. This case is not currently expected to occur
* because we don't use rotated. Enforce this restriction on all chips
* to facilitate testing.
*/
- if (surf->micro_tile_mode == RADEON_MICRO_MODE_ROTATED) {
+ if (surf->micro_tile_mode == RADEON_MICRO_MODE_RENDER) {
assert(!"rotate micro tile mode is unsupported");
return ADDR_ERROR;
}
@@ -1008,11 +1008,11 @@ gfx9_get_preferred_swizzle_mode(ADDR_HANDLE addrlib,
if (surf->micro_tile_mode == RADEON_MICRO_MODE_DISPLAY)
sin.preferredSwSet.sw_D = 1;
- else if (surf->micro_tile_mode == RADEON_MICRO_MODE_THIN)
+ else if (surf->micro_tile_mode == RADEON_MICRO_MODE_STANDARD)
sin.preferredSwSet.sw_S = 1;
else if (surf->micro_tile_mode == RADEON_MICRO_MODE_DEPTH)
sin.preferredSwSet.sw_Z = 1;
- else if (surf->micro_tile_mode == RADEON_MICRO_MODE_ROTATED)
+ else if (surf->micro_tile_mode == RADEON_MICRO_MODE_RENDER)
sin.preferredSwSet.sw_R = 1;
}
@@ -1634,7 +1634,7 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib,
case ADDR_SW_64KB_S_T:
case ADDR_SW_4KB_S_X:
case ADDR_SW_64KB_S_X:
- surf->micro_tile_mode = RADEON_MICRO_MODE_THIN;
+ surf->micro_tile_mode = RADEON_MICRO_MODE_STANDARD;
break;
/* D = display. */
@@ -1662,7 +1662,7 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib,
*/
assert(info->chip_class >= GFX10 ||
!"rotate micro tile mode is unsupported");
- surf->micro_tile_mode = RADEON_MICRO_MODE_ROTATED;
+ surf->micro_tile_mode = RADEON_MICRO_MODE_RENDER;
break;
/* Z = depth. */
diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h
index a552383caf0..56b2cb9aa5a 100644
--- a/src/amd/common/ac_surface.h
+++ b/src/amd/common/ac_surface.h
@@ -49,12 +49,14 @@ enum radeon_surf_mode {
RADEON_SURF_MODE_2D = 3,
};
-/* These are defined exactly like GB_TILE_MODEn.MICRO_TILE_MODE_NEW. */
+/* This describes D/S/Z/R swizzle modes.
+ * Defined in the GB_TILE_MODEn.MICRO_TILE_MODE_NEW order.
+ */
enum radeon_micro_mode {
RADEON_MICRO_MODE_DISPLAY = 0,
- RADEON_MICRO_MODE_THIN = 1,
+ RADEON_MICRO_MODE_STANDARD = 1,
RADEON_MICRO_MODE_DEPTH = 2,
- RADEON_MICRO_MODE_ROTATED = 3, /* gfx10+: render target */
+ RADEON_MICRO_MODE_RENDER = 3, /* gfx9 and older: rotated */
};
/* the first 16 bits are reserved for libdrm_radeon, don't use them */
diff --git a/src/gallium/drivers/radeonsi/si_clear.c b/src/gallium/drivers/radeonsi/si_clear.c
index 1e7aa443222..8c89c9be199 100644
--- a/src/gallium/drivers/radeonsi/si_clear.c
+++ b/src/gallium/drivers/radeonsi/si_clear.c
@@ -297,11 +297,11 @@ static void si_set_optimal_micro_tile_mode(struct si_screen *sscreen, struct si_
tex->surface.u.gfx9.surf.swizzle_mode &= ~0x3;
tex->surface.u.gfx9.surf.swizzle_mode += 2; /* D */
break;
- case RADEON_MICRO_MODE_THIN:
+ case RADEON_MICRO_MODE_STANDARD:
tex->surface.u.gfx9.surf.swizzle_mode &= ~0x3;
tex->surface.u.gfx9.surf.swizzle_mode += 1; /* S */
break;
- case RADEON_MICRO_MODE_ROTATED:
+ case RADEON_MICRO_MODE_RENDER:
tex->surface.u.gfx9.surf.swizzle_mode &= ~0x3;
tex->surface.u.gfx9.surf.swizzle_mode += 3; /* R */
break;
@@ -318,10 +318,10 @@ static void si_set_optimal_micro_tile_mode(struct si_screen *sscreen, struct si_
case RADEON_MICRO_MODE_DISPLAY:
tex->surface.u.legacy.tiling_index[0] = 10;
break;
- case RADEON_MICRO_MODE_THIN:
+ case RADEON_MICRO_MODE_STANDARD:
tex->surface.u.legacy.tiling_index[0] = 14;
break;
- case RADEON_MICRO_MODE_ROTATED:
+ case RADEON_MICRO_MODE_RENDER:
tex->surface.u.legacy.tiling_index[0] = 28;
break;
default: /* depth, thick */
@@ -343,7 +343,7 @@ static void si_set_optimal_micro_tile_mode(struct si_screen *sscreen, struct si_
break;
}
break;
- case RADEON_MICRO_MODE_THIN:
+ case RADEON_MICRO_MODE_STANDARD:
switch (tex->surface.bpe) {
case 1:
tex->surface.u.legacy.tiling_index[0] = 14;
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_surface.c b/src/gallium/winsys/radeon/drm/radeon_drm_surface.c
index 41d4bc15a00..6c2119d32b6 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_surface.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_surface.c
@@ -217,7 +217,7 @@ static void surf_drm_to_winsys(struct radeon_drm_winsys *ws,
set_micro_tile_mode(surf_ws, &ws->info);
surf_ws->is_displayable = surf_ws->is_linear ||
surf_ws->micro_tile_mode == RADEON_MICRO_MODE_DISPLAY ||
- surf_ws->micro_tile_mode == RADEON_MICRO_MODE_ROTATED;
+ surf_ws->micro_tile_mode == RADEON_MICRO_MODE_RENDER;
}
static void si_compute_cmask(const struct radeon_info *info,
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