Mesa (master): ac/surface: replace RADEON_SURF_OPTIMIZE_FOR_SPACE with !FORCE_SWIZZLE_MODE

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Module: Mesa
Branch: master
Commit: 3dc2ccc14c0e035368fea6ae3cce8c481f3c4ad2
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=3dc2ccc14c0e035368fea6ae3cce8c481f3c4ad2

Author: Marek Olšák <marek.olsak at amd.com>
Date:   Thu Apr 23 01:00:24 2020 -0400

ac/surface: replace RADEON_SURF_OPTIMIZE_FOR_SPACE with !FORCE_SWIZZLE_MODE

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4697>

---

 src/amd/common/ac_surface.c               | 2 +-
 src/amd/common/ac_surface.h               | 4 +++-
 src/amd/vulkan/radv_image.c               | 2 --
 src/gallium/drivers/r600/r600_texture.c   | 2 --
 src/gallium/drivers/radeonsi/si_texture.c | 8 ++++----
 5 files changed, 8 insertions(+), 10 deletions(-)

diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index 9b1ccca7371..943a9e13708 100644
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -661,7 +661,7 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
 	AddrSurfInfoIn.flags.opt4Space = !AddrSurfInfoIn.flags.tcCompatible &&
 					 !AddrSurfInfoIn.flags.fmask &&
 					 config->info.samples <= 1 &&
-					 (surf->flags & RADEON_SURF_OPTIMIZE_FOR_SPACE);
+					 !(surf->flags & RADEON_SURF_FORCE_SWIZZLE_MODE);
 
 	/* DCC notes:
 	 * - If we add MSAA support, keep in mind that CB can't decompress 8bpp
diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h
index a5e28c1a69c..77ddf2fc5e3 100644
--- a/src/amd/common/ac_surface.h
+++ b/src/amd/common/ac_surface.h
@@ -69,9 +69,11 @@ enum radeon_micro_mode {
 #define RADEON_SURF_DISABLE_DCC                 (1 << 22)
 /* gap */
 #define RADEON_SURF_IMPORTED                    (1 << 24)
-#define RADEON_SURF_OPTIMIZE_FOR_SPACE          (1 << 25)
+/* gap */
 #define RADEON_SURF_SHAREABLE                   (1 << 26)
 #define RADEON_SURF_NO_RENDER_TARGET            (1 << 27)
+/* Force a swizzle mode (gfx9+) or tile mode (gfx6-8).
+ * If this is not set, optimize for space. */
 #define RADEON_SURF_FORCE_SWIZZLE_MODE          (1 << 28)
 #define RADEON_SURF_NO_FMASK                    (1 << 29)
 #define RADEON_SURF_NO_HTILE                    (1 << 30)
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index 9633710bfdf..84eae33f433 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -449,8 +449,6 @@ radv_init_surface(struct radv_device *device,
 	    vk_format_is_compressed(image_format))
 		surface->flags |= RADEON_SURF_NO_RENDER_TARGET;
 
-	surface->flags |= RADEON_SURF_OPTIMIZE_FOR_SPACE;
-
 	if (!radv_use_dcc_for_image(device, image, pCreateInfo, image_format))
 		surface->flags |= RADEON_SURF_DISABLE_DCC;
 
diff --git a/src/gallium/drivers/r600/r600_texture.c b/src/gallium/drivers/r600/r600_texture.c
index 42cc09e8b76..3ffa7be7291 100644
--- a/src/gallium/drivers/r600/r600_texture.c
+++ b/src/gallium/drivers/r600/r600_texture.c
@@ -243,8 +243,6 @@ static int r600_init_surface(struct r600_common_screen *rscreen,
 		flags |= RADEON_SURF_SHAREABLE;
 	if (is_imported)
 		flags |= RADEON_SURF_IMPORTED | RADEON_SURF_SHAREABLE;
-	if (!(ptex->flags & R600_RESOURCE_FLAG_FORCE_TILING))
-		flags |= RADEON_SURF_OPTIMIZE_FOR_SPACE;
 
 	r = rscreen->ws->surface_init(rscreen->ws, ptex,
 				      flags, bpe, array_mode, surface);
diff --git a/src/gallium/drivers/radeonsi/si_texture.c b/src/gallium/drivers/radeonsi/si_texture.c
index bf919b75981..1ee4547f8da 100644
--- a/src/gallium/drivers/radeonsi/si_texture.c
+++ b/src/gallium/drivers/radeonsi/si_texture.c
@@ -289,8 +289,6 @@ static int si_init_surface(struct si_screen *sscreen, struct radeon_surf *surfac
       flags |= RADEON_SURF_SHAREABLE;
    if (is_imported)
       flags |= RADEON_SURF_IMPORTED | RADEON_SURF_SHAREABLE;
-   if (!(ptex->flags & SI_RESOURCE_FLAG_FORCE_MSAA_TILING))
-      flags |= RADEON_SURF_OPTIMIZE_FOR_SPACE;
    if (sscreen->debug_flags & DBG(NO_FMASK))
       flags |= RADEON_SURF_NO_FMASK;
 
@@ -299,9 +297,11 @@ static int si_init_surface(struct si_screen *sscreen, struct radeon_surf *surfac
       surface->micro_tile_mode = SI_RESOURCE_FLAG_MICRO_TILE_MODE_GET(ptex->flags);
    }
 
-   if (sscreen->info.chip_class >= GFX10 && (ptex->flags & SI_RESOURCE_FLAG_FORCE_MSAA_TILING)) {
+   if (ptex->flags & SI_RESOURCE_FLAG_FORCE_MSAA_TILING) {
       flags |= RADEON_SURF_FORCE_SWIZZLE_MODE;
-      surface->u.gfx9.surf.swizzle_mode = ADDR_SW_64KB_R_X;
+
+      if (sscreen->info.chip_class >= GFX10)
+         surface->u.gfx9.surf.swizzle_mode = ADDR_SW_64KB_R_X;
    }
 
    r = sscreen->ws->surface_init(sscreen->ws, ptex, flags, bpe, array_mode, surface);