Mesa (master): freedreno/a6xx: move blend-color to stateobj

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Module: Mesa
Branch: master
Commit: 880edb9dc5761aa19d89b2a40481e8c2771ff862
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=880edb9dc5761aa19d89b2a40481e8c2771ff862

Author: Rob Clark <robdclark at chromium.org>
Date:   Thu Apr 16 15:18:08 2020 -0700

freedreno/a6xx: move blend-color to stateobj

To reduce CP overhead for draws skipped in a bin.

Signed-off-by: Rob Clark <robdclark at chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4813>

---

 src/gallium/drivers/freedreno/a6xx/fd6_emit.c | 4 ++++
 src/gallium/drivers/freedreno/a6xx/fd6_emit.h | 1 +
 2 files changed, 5 insertions(+)

diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_emit.c b/src/gallium/drivers/freedreno/a6xx/fd6_emit.c
index 9d8ebbca446..ccd59f62876 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_emit.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_emit.c
@@ -1126,12 +1126,16 @@ fd6_emit_state(struct fd_ringbuffer *ring, struct fd6_emit *emit)
 
 	if (dirty & FD_DIRTY_BLEND_COLOR) {
 		struct pipe_blend_color *bcolor = &ctx->blend_color;
+		struct fd_ringbuffer *ring = fd_submit_new_ringbuffer(
+				emit->ctx->batch->submit, 5*4, FD_RINGBUFFER_STREAMING);
 
 		OUT_PKT4(ring, REG_A6XX_RB_BLEND_RED_F32, 4);
 		OUT_RING(ring, A6XX_RB_BLEND_RED_F32(bcolor->color[0]));
 		OUT_RING(ring, A6XX_RB_BLEND_GREEN_F32(bcolor->color[1]));
 		OUT_RING(ring, A6XX_RB_BLEND_BLUE_F32(bcolor->color[2]));
 		OUT_RING(ring, A6XX_RB_BLEND_ALPHA_F32(bcolor->color[3]));
+
+		fd6_emit_take_group(emit, ring, FD6_GROUP_BLEND_COLOR, ENABLE_DRAW);
 	}
 
 	needs_border |= fd6_emit_combined_textures(ring, emit, PIPE_SHADER_VERTEX, vs);
diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_emit.h b/src/gallium/drivers/freedreno/a6xx/fd6_emit.h
index d0642cb564e..32968c819d5 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_emit.h
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_emit.h
@@ -64,6 +64,7 @@ enum fd6_state_id {
 	FD6_GROUP_ZSA,
 	FD6_GROUP_BLEND,
 	FD6_GROUP_SCISSOR,
+	FD6_GROUP_BLEND_COLOR,
 };
 
 #define ENABLE_ALL (CP_SET_DRAW_STATE__0_BINNING | CP_SET_DRAW_STATE__0_GMEM | CP_SET_DRAW_STATE__0_SYSMEM)