Mesa (master): radv: increase minimum NGG vertex count requirement per workgroup on GFX 10.3

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Module: Mesa
Branch: master
Commit: 8b3682310ce7aec964f4f2529f6a255ce87fd760
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=8b3682310ce7aec964f4f2529f6a255ce87fd760

Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date:   Tue Aug  4 10:56:51 2020 +0200

radv: increase minimum NGG vertex count requirement per workgroup on GFX 10.3

Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6168>

---

 src/amd/vulkan/radv_pipeline.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 6d4df832fe5..acca6c01315 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -1939,6 +1939,7 @@ gfx10_get_ngg_info(const struct radv_pipeline_key *key,
 	unsigned gsprim_lds_size = 0;
 
 	/* All these are per subgroup: */
+	const unsigned min_esverts = pipeline->device->physical_device->rad_info.chip_class >= GFX10_3 ? 29 : 24;
 	bool max_vert_out_per_gs_instance = false;
 	unsigned max_esverts_base = 256;
 	unsigned max_gsprims_base = 128; /* default prim group size clamp */
@@ -2064,7 +2065,7 @@ gfx10_get_ngg_info(const struct radv_pipeline_key *key,
 	}
 
 	/* Hardware restriction: minimum value of max_esverts */
-	max_esverts = MAX2(max_esverts, 23 + max_verts_per_prim);
+	max_esverts = MAX2(max_esverts, min_esverts - 1 + max_verts_per_prim);
 
 	unsigned max_out_vertices =
 		max_vert_out_per_gs_instance ? gs_info->gs.vertices_out :
@@ -2101,7 +2102,7 @@ gfx10_get_ngg_info(const struct radv_pipeline_key *key,
 
 	pipeline->graphics.esgs_ring_size = ngg->esgs_ring_size;
 
-	assert(ngg->hw_max_esverts >= 24); /* HW limitation */
+	assert(ngg->hw_max_esverts >= min_esverts); /* HW limitation */
 }
 
 static void