Mesa (master): st/mesa: Treat vertex outputs absent in outputMapping as zero in mesa_to_tgsi

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Module: Mesa
Branch: master
Commit: 782ba8d3ae55af392da8ca829f3a185c10bbecfc
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=782ba8d3ae55af392da8ca829f3a185c10bbecfc

Author: Danylo Piliaiev <danylo.piliaiev at globallogic.com>
Date:   Wed Aug  5 18:07:06 2020 +0300

st/mesa: Treat vertex outputs absent in outputMapping as zero in mesa_to_tgsi

After updating vertex outputs being written based on optimized NIR, they may
go out of sync with outputs in mesa IR. Which is translated to TGSI and used
together with NIR if draw doesn't have llvm.

It's much easier to treat such outputs as zero because there is no pass to
entirely get rid of them.

Similar to eeab9c93db84e5759145891e8fdde66a5cdcf917 but now for outputs.

Fixes: d684fb37bfbc47d098158cb03c0672119a4469fe
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3365
Signed-off-by: Danylo Piliaiev <danylo.piliaiev at globallogic.com>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6187>

---

 src/mesa/state_tracker/st_mesa_to_tgsi.c | 17 ++++++++++++-----
 1 file changed, 12 insertions(+), 5 deletions(-)

diff --git a/src/mesa/state_tracker/st_mesa_to_tgsi.c b/src/mesa/state_tracker/st_mesa_to_tgsi.c
index 6fe8f851757..dca9acb3f31 100644
--- a/src/mesa/state_tracker/st_mesa_to_tgsi.c
+++ b/src/mesa/state_tracker/st_mesa_to_tgsi.c
@@ -97,9 +97,12 @@ dst_register(struct st_translate *t, gl_register_file file, GLuint index)
       else
          assert(index < VARYING_SLOT_MAX);
 
-      assert(t->outputMapping[index] < ARRAY_SIZE(t->outputs));
-
-      return t->outputs[t->outputMapping[index]];
+      if (t->outputMapping[index] < ARRAY_SIZE(t->outputs))
+         return t->outputs[t->outputMapping[index]];
+      else {
+         assert(t->procType == PIPE_SHADER_VERTEX);
+         return ureg_dst(ureg_DECL_constant(t->ureg, 0));
+      }
 
    case PROGRAM_ADDRESS:
       return t->address[index];
@@ -149,8 +152,12 @@ src_register(struct st_translate *t,
       }
 
    case PROGRAM_OUTPUT:
-      assert(t->outputMapping[index] < ARRAY_SIZE(t->outputs));
-      return ureg_src(t->outputs[t->outputMapping[index]]); /* not needed? */
+      if (t->outputMapping[index] < ARRAY_SIZE(t->outputs))
+         return ureg_src(t->outputs[t->outputMapping[index]]);
+      else {
+         assert(t->procType == PIPE_SHADER_VERTEX);
+         return ureg_DECL_constant(t->ureg, 0);
+      }
 
    case PROGRAM_ADDRESS:
       return ureg_src(t->address[index]);