Mesa (staging/20.2): anv/nir: Unify inputs_read/outputs_written between geometry stages
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Tue Aug 18 17:43:32 UTC 2020
Module: Mesa
Branch: staging/20.2
Commit: 55ef5d5a227bd7eb115b9fe048d7e06277430b91
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=55ef5d5a227bd7eb115b9fe048d7e06277430b91
Author: Danylo Piliaiev <danylo.piliaiev at globallogic.com>
Date: Mon Jul 27 18:00:41 2020 +0300
anv/nir: Unify inputs_read/outputs_written between geometry stages
inputs_read/outputs_written are used for a shader stage to
determine the layout of input and output storage. Adjacent stages must
agree on the layout, so adjacent input/output bitfields must match.
Most of the time, cross-stage optimizations make that happen anyway,
but there are some cases (with special values like clip distances and
point size) where this doesn't happen.
Fixes crashes in dEQP-VK.subgroups.*.framebuffer.*_tess_eval
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3210
Cc: <mesa-stable at lists.freedesktop.org>
Signed-off-by: Danylo Piliaiev <danylo.piliaiev at globallogic.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6102>
(cherry picked from commit 2701f887fc376202577ad942c20a7284b12823f3)
---
.pick_status.json | 2 +-
src/intel/vulkan/anv_pipeline.c | 29 +++++++++++++++++++++++++++--
2 files changed, 28 insertions(+), 3 deletions(-)
diff --git a/.pick_status.json b/.pick_status.json
index df545ae3961..e06d68df19d 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -22,7 +22,7 @@
"description": "anv/nir: Unify inputs_read/outputs_written between geometry stages",
"nominated": true,
"nomination_type": 0,
- "resolution": 0,
+ "resolution": 1,
"master_sha": null,
"because_sha": null
},
diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c
index 1b7c09f35a5..845451f7fc2 100644
--- a/src/intel/vulkan/anv_pipeline.c
+++ b/src/intel/vulkan/anv_pipeline.c
@@ -1505,14 +1505,39 @@ anv_pipeline_compile_graphics(struct anv_graphics_pipeline *pipeline,
void *stage_ctx = ralloc_context(NULL);
+ anv_pipeline_lower_nir(&pipeline->base, stage_ctx, &stages[s], layout);
+
+ if (prev_stage && compiler->glsl_compiler_options[s].NirOptions->unify_interfaces) {
+ prev_stage->nir->info.outputs_written |= stages[s].nir->info.inputs_read &
+ ~(VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER);
+ stages[s].nir->info.inputs_read |= prev_stage->nir->info.outputs_written &
+ ~(VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER);
+ prev_stage->nir->info.patch_outputs_written |= stages[s].nir->info.patch_inputs_read;
+ stages[s].nir->info.patch_inputs_read |= prev_stage->nir->info.patch_outputs_written;
+ }
+
+ ralloc_free(stage_ctx);
+
+ stages[s].feedback.duration += os_time_get_nano() - stage_start;
+
+ prev_stage = &stages[s];
+ }
+
+ prev_stage = NULL;
+ for (unsigned s = 0; s < MESA_SHADER_STAGES; s++) {
+ if (!stages[s].entrypoint)
+ continue;
+
+ int64_t stage_start = os_time_get_nano();
+
+ void *stage_ctx = ralloc_context(NULL);
+
nir_xfb_info *xfb_info = NULL;
if (s == MESA_SHADER_VERTEX ||
s == MESA_SHADER_TESS_EVAL ||
s == MESA_SHADER_GEOMETRY)
xfb_info = nir_gather_xfb_info(stages[s].nir, stage_ctx);
- anv_pipeline_lower_nir(&pipeline->base, stage_ctx, &stages[s], layout);
-
switch (s) {
case MESA_SHADER_VERTEX:
anv_pipeline_compile_vs(compiler, stage_ctx, pipeline,
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