Mesa (master): st/mesa: increase size of gl_register_file bitfields

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Module: Mesa
Branch: master
Commit: 090239ea6b7fee79643960cbc361e4ec577c7be9
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=090239ea6b7fee79643960cbc361e4ec577c7be9

Author: Charmaine Lee <charmainel at vmware.com>
Date:   Thu Aug 20 17:11:22 2020 -0700

st/mesa: increase size of gl_register_file bitfields

Bump up the size of the bitfields for gl_register_file type for MSVC.
Also add ASSERT_BITFIELD_SIZE check where this bitfield is used.

Fixes spec at arb_shader_atomic_counter_ops tests in MSVC.

Reviewed-by: Neha Bhende <bhenden at vmware.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6417>

---

 src/mesa/state_tracker/st_glsl_to_tgsi.cpp       | 2 ++
 src/mesa/state_tracker/st_glsl_to_tgsi_private.h | 4 ++--
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index 1c644163716..7d8f6fc3b25 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -6622,7 +6622,9 @@ st_translate_program(
    assert(numOutputs <= ARRAY_SIZE(t->outputs));
 
    ASSERT_BITFIELD_SIZE(st_src_reg, type, GLSL_TYPE_ERROR);
+   ASSERT_BITFIELD_SIZE(st_src_reg, file, PROGRAM_FILE_MAX);
    ASSERT_BITFIELD_SIZE(st_dst_reg, type, GLSL_TYPE_ERROR);
+   ASSERT_BITFIELD_SIZE(st_dst_reg, file, PROGRAM_FILE_MAX);
    ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction, tex_type, GLSL_TYPE_ERROR);
    ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction, image_format, PIPE_FORMAT_COUNT);
    ASSERT_BITFIELD_SIZE(glsl_to_tgsi_instruction, tex_target,
diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi_private.h b/src/mesa/state_tracker/st_glsl_to_tgsi_private.h
index 0b24e2ea774..19dfa952e10 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi_private.h
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi_private.h
@@ -65,7 +65,7 @@ public:
    unsigned abs:1;
    enum glsl_base_type type:6; /** GLSL_TYPE_* from GLSL IR (enum glsl_base_type) */
    unsigned has_index2:1;
-   gl_register_file file:5; /**< PROGRAM_* from Mesa */
+   gl_register_file file:6; /**< PROGRAM_* from Mesa */
    /*
     * Is this the second half of a double register pair?
     * currently used for input mapping only.
@@ -105,7 +105,7 @@ public:
 
    int32_t index; /**< temporary index, VERT_ATTRIB_*, VARYING_SLOT_*, etc. */
    int16_t index2D;
-   gl_register_file file:5; /**< PROGRAM_* from Mesa */
+   gl_register_file file:6; /**< PROGRAM_* from Mesa */
    unsigned writemask:4; /**< Bitfield of WRITEMASK_[XYZW] */
    enum glsl_base_type type:6; /** GLSL_TYPE_* from GLSL IR (enum glsl_base_type) */
    unsigned has_index2:1;