Mesa (master): zink: revert to old load_ubo implementation
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gitlab-mirror at kemper.freedesktop.org
Tue Dec 1 18:31:37 UTC 2020
Module: Mesa
Branch: master
Commit: 8fca21d3e70a8f0b09021fddd7db00f8faeae68d
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8fca21d3e70a8f0b09021fddd7db00f8faeae68d
Author: Erik Faye-Lund <erik.faye-lund at collabora.com>
Date: Thu Nov 26 20:54:02 2020 +0100
zink: revert to old load_ubo implementation
It turns out, the load_ubo to load_ubo_vec4 implementation isn't quite
enough for us, for a few reasons:
1. We use a single array of uvec4s for our UBOs, and to handle 64-bit
values in UBOs, we need further lowering.
2. The whole vec4 stuff seems a bit hard to reconsile with glsl 4.3
packing as well as PackedDriverUniformStorage.
In addition to the above, this fixes several piglit tests that *aren't*
part of quick_gl, which is what I've been running. So this doesn't even
work correctly right now.
So let's go back to what we had before instead.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3643
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz at gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7858>
---
.../drivers/zink/nir_to_spirv/nir_to_spirv.c | 52 ----------------------
src/gallium/drivers/zink/zink_compiler.c | 1 -
2 files changed, 53 deletions(-)
diff --git a/src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c b/src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c
index d990bdc9af6..09ff563e46b 100644
--- a/src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c
+++ b/src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c
@@ -1613,54 +1613,6 @@ emit_load_ubo(struct ntv_context *ctx, nir_intrinsic_instr *intr)
store_dest(ctx, &intr->dest, result, nir_type_uint);
}
-static void
-emit_load_ubo_vec4(struct ntv_context *ctx, nir_intrinsic_instr *intr)
-{
- ASSERTED nir_const_value *const_block_index = nir_src_as_const_value(intr->src[0]);
- assert(const_block_index); // no dynamic indexing for now
-
- SpvId offset = get_src(ctx, &intr->src[1]);
- SpvId uvec4_type = get_uvec_type(ctx, 32, 4);
- SpvId pointer_type = spirv_builder_type_pointer(&ctx->builder,
- SpvStorageClassUniform,
- uvec4_type);
-
- SpvId member = emit_uint_const(ctx, 32, 0);
- SpvId offsets[] = { member, offset };
- SpvId ptr = spirv_builder_emit_access_chain(&ctx->builder, pointer_type,
- ctx->ubos[const_block_index->u32],
- offsets, ARRAY_SIZE(offsets));
- SpvId result = spirv_builder_emit_load(&ctx->builder, uvec4_type, ptr);
-
- SpvId type = get_dest_uvec_type(ctx, &intr->dest);
- unsigned num_components = nir_dest_num_components(intr->dest);
- if (num_components == 1) {
- uint32_t components[] = { 0 };
- result = spirv_builder_emit_composite_extract(&ctx->builder,
- type,
- result, components,
- 1);
- } else if (num_components < 4) {
- SpvId constituents[num_components];
- SpvId uint_type = spirv_builder_type_uint(&ctx->builder, 32);
- for (uint32_t i = 0; i < num_components; ++i)
- constituents[i] = spirv_builder_emit_composite_extract(&ctx->builder,
- uint_type,
- result, &i,
- 1);
-
- result = spirv_builder_emit_composite_construct(&ctx->builder,
- type,
- constituents,
- num_components);
- }
-
- if (nir_dest_bit_size(intr->dest) == 1)
- result = uvec_to_bvec(ctx, result, num_components);
-
- store_dest(ctx, &intr->dest, result, nir_type_uint);
-}
-
static void
emit_discard(struct ntv_context *ctx, nir_intrinsic_instr *intr)
{
@@ -1813,10 +1765,6 @@ emit_intrinsic(struct ntv_context *ctx, nir_intrinsic_instr *intr)
emit_load_ubo(ctx, intr);
break;
- case nir_intrinsic_load_ubo_vec4:
- emit_load_ubo_vec4(ctx, intr);
- break;
-
case nir_intrinsic_discard:
emit_discard(ctx, intr);
break;
diff --git a/src/gallium/drivers/zink/zink_compiler.c b/src/gallium/drivers/zink/zink_compiler.c
index bd351609763..7e77bb1d937 100644
--- a/src/gallium/drivers/zink/zink_compiler.c
+++ b/src/gallium/drivers/zink/zink_compiler.c
@@ -267,7 +267,6 @@ zink_shader_create(struct zink_screen *screen, struct nir_shader *nir,
*/
if (nir->num_uniforms)
NIR_PASS_V(nir, nir_lower_uniforms_to_ubo, 16);
- NIR_PASS_V(nir, nir_lower_ubo_vec4);
NIR_PASS_V(nir, nir_lower_clip_halfz);
if (nir->info.stage < MESA_SHADER_FRAGMENT)
have_psiz = check_psiz(nir);
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