Mesa (master): radv: set the predication boolean as 32-bit if necessary

[GitLab Mirror]

Module: Mesa
Branch: master
Commit: 3494551d081820b1e5835fb46c8e98564ce855f6
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=3494551d081820b1e5835fb46c8e98564ce855f6

Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date:   Thu Dec  3 12:42:12 2020 +0100

radv: set the predication boolean as 32-bit if necessary

CTS is missing tests.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7897>

---

 src/amd/common/sid.h                  | 1 +
 src/amd/vulkan/radv_cmd_buffer.c      | 8 ++++++--
 src/amd/vulkan/radv_meta_fast_clear.c | 3 ++-
 src/amd/vulkan/radv_private.h         | 4 +++-
 src/amd/vulkan/si_cmd_buffer.c        | 7 +++++--
 5 files changed, 17 insertions(+), 6 deletions(-)

diff --git a/src/amd/common/sid.h b/src/amd/common/sid.h
index a55598ce9c9..be11c712cce 100644
--- a/src/amd/common/sid.h
+++ b/src/amd/common/sid.h
@@ -81,6 +81,7 @@
 #define PREDICATION_OP_ZPASS     0x1
 #define PREDICATION_OP_PRIMCOUNT 0x2
 #define PREDICATION_OP_BOOL64    0x3
+#define PREDICATION_OP_BOOL32    0x4
 
 #define PRED_OP(x) ((x) << 16)
 
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 4ccb86b8178..cf6652d918f 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -6527,6 +6527,7 @@ void radv_CmdBeginConditionalRenderingEXT(
 	RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
 	RADV_FROM_HANDLE(radv_buffer, buffer, pConditionalRenderingBegin->buffer);
 	struct radeon_cmdbuf *cs = cmd_buffer->cs;
+	unsigned pred_op = PREDICATION_OP_BOOL32;
 	bool draw_visible = true;
 	uint64_t va;
 
@@ -6592,14 +6593,16 @@ void radv_CmdBeginConditionalRenderingEXT(
 		radeon_emit(cs, 0);
 
 		va = pred_va;
+		pred_op = PREDICATION_OP_BOOL64;
 	}
 
 	/* Enable predication for this command buffer. */
-	si_emit_set_predication_state(cmd_buffer, draw_visible, va);
+	si_emit_set_predication_state(cmd_buffer, draw_visible, pred_op, va);
 	cmd_buffer->state.predicating = true;
 
 	/* Store conditional rendering user info. */
 	cmd_buffer->state.predication_type = draw_visible;
+	cmd_buffer->state.predication_op = pred_op;
 	cmd_buffer->state.predication_va = va;
 }
 
@@ -6609,11 +6612,12 @@ void radv_CmdEndConditionalRenderingEXT(
 	RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
 
 	/* Disable predication for this command buffer. */
-	si_emit_set_predication_state(cmd_buffer, false, 0);
+	si_emit_set_predication_state(cmd_buffer, false, 0, 0);
 	cmd_buffer->state.predicating = false;
 
 	/* Reset conditional rendering user info. */
 	cmd_buffer->state.predication_type = -1;
+	cmd_buffer->state.predication_op = 0;
 	cmd_buffer->state.predication_va = 0;
 }
 
diff --git a/src/amd/vulkan/radv_meta_fast_clear.c b/src/amd/vulkan/radv_meta_fast_clear.c
index 1403e35b4f9..e20d561c5d7 100644
--- a/src/amd/vulkan/radv_meta_fast_clear.c
+++ b/src/amd/vulkan/radv_meta_fast_clear.c
@@ -572,7 +572,7 @@ radv_emit_set_predication_state_from_image(struct radv_cmd_buffer *cmd_buffer,
 		va += pred_offset;
 	}
 
-	si_emit_set_predication_state(cmd_buffer, true, va);
+	si_emit_set_predication_state(cmd_buffer, true, PREDICATION_OP_BOOL64, va);
 }
 
 static void
@@ -771,6 +771,7 @@ radv_emit_color_decompress(struct radv_cmd_buffer *cmd_buffer,
 			/* Restore previous conditional rendering user state. */
 			si_emit_set_predication_state(cmd_buffer,
 						      cmd_buffer->state.predication_type,
+						      cmd_buffer->state.predication_op,
 						      cmd_buffer->state.predication_va);
 		}
 	}
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 80f8f04d809..82cddae8b29 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -1376,6 +1376,7 @@ struct radv_cmd_state {
 	bool dma_is_busy;
 
 	/* Conditional rendering info. */
+	uint8_t predication_op; /* 32-bit or 64-bit predicate value */
 	int predication_type; /* -1: disabled, 0: normal, 1: inverted */
 	uint64_t predication_va;
 
@@ -1513,7 +1514,8 @@ void si_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
 			    uint64_t gfx9_eop_bug_va);
 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
 void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer,
-				   bool inverted, uint64_t va);
+				   bool draw_visible, unsigned pred_op,
+				   uint64_t va);
 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
 			   uint64_t src_va, uint64_t dest_va,
 			   uint64_t size);
diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
index c20a39a01bb..0d83ca2d8cd 100644
--- a/src/amd/vulkan/si_cmd_buffer.c
+++ b/src/amd/vulkan/si_cmd_buffer.c
@@ -1532,12 +1532,15 @@ si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer)
 /* sets the CP predication state using a boolean stored at va */
 void
 si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer,
-			      bool draw_visible, uint64_t va)
+			      bool draw_visible, unsigned pred_op, uint64_t va)
 {
 	uint32_t op = 0;
 
 	if (va) {
-		op = PRED_OP(PREDICATION_OP_BOOL64);
+		assert(pred_op == PREDICATION_OP_BOOL32 ||
+		       pred_op == PREDICATION_OP_BOOL64);
+
+		op = PRED_OP(pred_op);
 
 		/* PREDICATION_DRAW_VISIBLE means that if the 32-bit value is
 		 * zero, all rendering commands are discarded. Otherwise, they