Mesa (master): turnip: always set LRZ registers to zero for 3d clear/blit
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Tue Dec 8 18:47:34 UTC 2020
Module: Mesa
Branch: master
Commit: fa16e66a3f4bf6f7eaef82c1770239be9dd824da
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=fa16e66a3f4bf6f7eaef82c1770239be9dd824da
Author: Jonathan Marek <jonathan at marek.ca>
Date: Thu Dec 3 00:05:37 2020 -0500
turnip: always set LRZ registers to zero for 3d clear/blit
Apparently LRZ will be read/written regardless of depth being enabled or
not, so we have to make sure these registers are zero.
Fixes: 1d83f5ae8435 ("turnip: disable LRZ on vkCmdClearattachments() 3D fallback path")
Signed-off-by: Jonathan Marek <jonathan at marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7899>
---
src/freedreno/vulkan/tu_clear_blit.c | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/src/freedreno/vulkan/tu_clear_blit.c b/src/freedreno/vulkan/tu_clear_blit.c
index 8c29fb39206..97239214beb 100644
--- a/src/freedreno/vulkan/tu_clear_blit.c
+++ b/src/freedreno/vulkan/tu_clear_blit.c
@@ -847,6 +847,9 @@ r3d_setup(struct tu_cmd_buffer *cmd,
tu_cs_emit_regs(cs, A6XX_RB_SRGB_CNTL(vk_format_is_srgb(vk_format)));
tu_cs_emit_regs(cs, A6XX_SP_SRGB_CNTL(vk_format_is_srgb(vk_format)));
+ tu_cs_emit_regs(cs, A6XX_GRAS_LRZ_CNTL(0));
+ tu_cs_emit_regs(cs, A6XX_RB_LRZ_CNTL(0));
+
if (cmd->state.predication_active) {
tu_cs_emit_pkt7(cs, CP_DRAW_PRED_ENABLE_LOCAL, 1);
tu_cs_emit(cs, 0);
@@ -2014,10 +2017,8 @@ tu_clear_sysmem_attachments(struct tu_cmd_buffer *cmd,
.component_enable = COND(clear_rts & (1 << i), 0xf)));
}
- if (z_clear) {
- tu_cs_emit_regs(cs, A6XX_GRAS_LRZ_CNTL(0));
- tu_cs_emit_regs(cs, A6XX_RB_LRZ_CNTL(0));
- }
+ tu_cs_emit_regs(cs, A6XX_GRAS_LRZ_CNTL(0));
+ tu_cs_emit_regs(cs, A6XX_RB_LRZ_CNTL(0));
tu_cs_emit_regs(cs, A6XX_RB_DEPTH_PLANE_CNTL());
tu_cs_emit_regs(cs, A6XX_RB_DEPTH_CNTL(
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