Mesa (master): intel/blorp: Drop support for STC_CCS resolves
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Thu Dec 10 22:51:06 UTC 2020
Module: Mesa
Branch: master
Commit: 574429f9528734f078c8c3a56232ba66fa818913
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=574429f9528734f078c8c3a56232ba66fa818913
Author: Nanley Chery <nanley.g.chery at intel.com>
Date: Wed Dec 9 15:11:45 2020 -0800
intel/blorp: Drop support for STC_CCS resolves
There are no users of this feature.
Reverts the following commits:
* 87c57b8dae954c7de6a499506a4161f69076ce67 (effectively)
* 53d472df24d4bc05359120df0615321318922d6d
* 9ab0e92cff8bb8336cebd9dc68d02d7451ad78e1
Reviewed-by: Sagar Ghuge <sagar.ghuge at intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8021>
---
src/intel/blorp/blorp.c | 30 ----------------
src/intel/blorp/blorp.h | 4 ---
src/intel/blorp/blorp_genX_exec.h | 73 +++++++--------------------------------
3 files changed, 12 insertions(+), 95 deletions(-)
diff --git a/src/intel/blorp/blorp.c b/src/intel/blorp/blorp.c
index 37edfe0a178..0c0b70f94f1 100644
--- a/src/intel/blorp/blorp.c
+++ b/src/intel/blorp/blorp.c
@@ -383,33 +383,3 @@ blorp_hiz_op(struct blorp_batch *batch, struct blorp_surf *surf,
batch->blorp->exec(batch, ¶ms);
}
}
-
-void
-blorp_hiz_stencil_op(struct blorp_batch *batch, struct blorp_surf *stencil,
- uint32_t level, uint32_t start_layer,
- uint32_t num_layers, enum isl_aux_op op)
-{
- struct blorp_params params;
- blorp_params_init(¶ms);
-
- params.hiz_op = op;
- params.full_surface_hiz_op = true;
-
- for (uint32_t a = 0; a < num_layers; a++) {
- const uint32_t layer = start_layer + a;
-
- brw_blorp_surface_info_init(batch->blorp, ¶ms.stencil, stencil, level,
- layer, stencil->surf->format, true);
- params.x1 = minify(params.stencil.surf.logical_level0_px.width,
- params.stencil.view.base_level);
- params.y1 = minify(params.stencil.surf.logical_level0_px.height,
- params.stencil.view.base_level);
- params.dst.surf.samples = params.stencil.surf.samples;
- params.dst.surf.logical_level0_px =
- params.stencil.surf.logical_level0_px;
- params.dst.view = params.stencil.view;
- params.num_samples = params.stencil.surf.samples;
-
- batch->blorp->exec(batch, ¶ms);
- }
-}
diff --git a/src/intel/blorp/blorp.h b/src/intel/blorp/blorp.h
index f8d8b0b8420..dd0d4c8ce13 100644
--- a/src/intel/blorp/blorp.h
+++ b/src/intel/blorp/blorp.h
@@ -245,10 +245,6 @@ blorp_hiz_op(struct blorp_batch *batch, struct blorp_surf *surf,
uint32_t level, uint32_t start_layer, uint32_t num_layers,
enum isl_aux_op op);
-void
-blorp_hiz_stencil_op(struct blorp_batch *batch, struct blorp_surf *stencil,
- uint32_t level, uint32_t start_layer,
- uint32_t num_layers, enum isl_aux_op op);
#ifdef __cplusplus
} /* end extern "C" */
#endif /* __cplusplus */
diff --git a/src/intel/blorp/blorp_genX_exec.h b/src/intel/blorp/blorp_genX_exec.h
index c37078aea5a..5eb4419d7f2 100644
--- a/src/intel/blorp/blorp_genX_exec.h
+++ b/src/intel/blorp/blorp_genX_exec.h
@@ -1715,18 +1715,11 @@ blorp_emit_gen8_hiz_op(struct blorp_batch *batch,
*/
assert(params->depth.enabled || params->stencil.enabled);
- /* The stencil buffer should only be enabled on GEN == 12, if a fast clear
- * or full resolve operation is requested. On rest of the GEN, if a fast
- * clear operation is requested.
+ /* The stencil buffer should only be enabled if a fast clear operation is
+ * requested.
*/
- if (params->stencil.enabled) {
-#if GEN_GEN >= 12
- assert(params->hiz_op == ISL_AUX_OP_FAST_CLEAR ||
- params->hiz_op == ISL_AUX_OP_FULL_RESOLVE);
-#else
+ if (params->stencil.enabled)
assert(params->hiz_op == ISL_AUX_OP_FAST_CLEAR);
-#endif
- }
/* From the BDW PRM Volume 2, 3DSTATE_WM_HZ_OP:
*
@@ -1753,38 +1746,14 @@ blorp_emit_gen8_hiz_op(struct blorp_batch *batch,
blorp_emit_cc_viewport(batch);
}
- if (GEN_GEN >= 12 && params->stencil.enabled &&
- params->hiz_op == ISL_AUX_OP_FULL_RESOLVE) {
- /* GEN:BUG:1605967699
- *
- * This workaround requires that the Force Thread Dispatch Enable flag
- * needs to be set to ForceOFF on the first WM_HZ_OP state cycle
- * (followed by a CS Stall):
- *
- * "Workaround: There is a potential software workaround for the
- * issue by doing these 2 steps 1) setting the force thread dispatch
- * enable(bits 20:19) in the 3dstate_WM_body state to be set to
- * Force_OFF (value of 1) along with the first WM_HZ_OP state cycle.
- * The second WM_HZ_OP state which is required by programming
- * sequencing to complete the HZ_OP operation can reprogram the
- * 3dstate_WM_body to set to NORMAL(value of 0)."
- */
- blorp_emit(batch, GENX(3DSTATE_WM), wm) {
- wm.ForceThreadDispatchEnable = ForceOff;
- }
- blorp_emit(batch, GENX(PIPE_CONTROL), pipe) {
- pipe.CommandStreamerStallEnable = true;
- }
- } else {
- /* According to the SKL PRM formula for WM_INT::ThreadDispatchEnable, the
- * 3DSTATE_WM::ForceThreadDispatchEnable field can force WM thread dispatch
- * even when WM_HZ_OP is active. However, WM thread dispatch is normally
- * disabled for HiZ ops and it appears that force-enabling it can lead to
- * GPU hangs on at least Skylake. Since we don't know the current state of
- * the 3DSTATE_WM packet, just emit a dummy one prior to 3DSTATE_WM_HZ_OP.
- */
- blorp_emit(batch, GENX(3DSTATE_WM), wm);
- }
+ /* According to the SKL PRM formula for WM_INT::ThreadDispatchEnable, the
+ * 3DSTATE_WM::ForceThreadDispatchEnable field can force WM thread dispatch
+ * even when WM_HZ_OP is active. However, WM thread dispatch is normally
+ * disabled for HiZ ops and it appears that force-enabling it can lead to
+ * GPU hangs on at least Skylake. Since we don't know the current state of
+ * the 3DSTATE_WM packet, just emit a dummy one prior to 3DSTATE_WM_HZ_OP.
+ */
+ blorp_emit(batch, GENX(3DSTATE_WM), wm);
/* If we can't alter the depth stencil config and multiple layers are
* involved, the HiZ op will fail. This is because the op requires that a
@@ -1806,13 +1775,7 @@ blorp_emit_gen8_hiz_op(struct blorp_batch *batch,
break;
case ISL_AUX_OP_FULL_RESOLVE:
assert(params->full_surface_hiz_op);
- hzp.DepthBufferResolveEnable = params->depth.enabled;
-#if GEN_GEN >= 12
- if (params->stencil.enabled) {
- assert(params->stencil.aux_usage == ISL_AUX_USAGE_STC_CCS);
- hzp.StencilBufferResolveEnable = true;
- }
-#endif
+ hzp.DepthBufferResolveEnable = true;
break;
case ISL_AUX_OP_AMBIGUATE:
assert(params->full_surface_hiz_op);
@@ -1846,18 +1809,6 @@ blorp_emit_gen8_hiz_op(struct blorp_batch *batch,
pc.Address = blorp_get_workaround_address(batch);
}
-
- if (GEN_GEN >= 12 && params->stencil.enabled &&
- params->hiz_op == ISL_AUX_OP_FULL_RESOLVE) {
- /* GEN:BUG:1605967699
- *
- * The second WM_HZ_OP state which is required by programming
- * sequencing to complete the HZ_OP operation can reprogram the
- * 3dstate_WM_body to set to NORMAL(value of 0)."
- */
- blorp_emit(batch, GENX(3DSTATE_WM), wm);
- }
-
blorp_emit(batch, GENX(3DSTATE_WM_HZ_OP), hzp);
}
#endif
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