Mesa (master): aco: Add tests for subdword register allocation

GitLab Mirror gitlab-mirror at kemper.freedesktop.org
Tue Dec 29 19:05:36 UTC 2020


Module: Mesa
Branch: master
Commit: b841b4fde83e33cdcd6792996064d1cd27b56ab9
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=b841b4fde83e33cdcd6792996064d1cd27b56ab9

Author: Tony Wasserka <tony.wasserka at gmx.de>
Date:   Mon Nov  2 18:16:56 2020 +0100

aco: Add tests for subdword register allocation

Reviewed-by: Daniel Schürmann <daniel at schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7461>

---

 src/amd/compiler/aco_validate.cpp        |  2 +-
 src/amd/compiler/tests/helpers.cpp       | 19 ++++++++++
 src/amd/compiler/tests/helpers.h         |  5 +++
 src/amd/compiler/tests/meson.build       |  1 +
 src/amd/compiler/tests/test_regalloc.cpp | 60 ++++++++++++++++++++++++++++++++
 5 files changed, 86 insertions(+), 1 deletion(-)

diff --git a/src/amd/compiler/aco_validate.cpp b/src/amd/compiler/aco_validate.cpp
index ae7e8a93ed2..e4ed3f0704c 100644
--- a/src/amd/compiler/aco_validate.cpp
+++ b/src/amd/compiler/aco_validate.cpp
@@ -351,7 +351,7 @@ bool validate_ir(Program* program)
                   has_literal |= op.isLiteral();
                }
 
-               check(!is_subdword || !has_const_sgpr || program->chip_class >= GFX9,
+               check(!is_subdword || !has_const_sgpr || program->chip_class >= GFX9 || instr->opcode == aco_opcode::p_unit_test,
                      "Sub-dword pseudo instructions can only take constants or SGPRs on GFX9+", instr.get());
             }
 
diff --git a/src/amd/compiler/tests/helpers.cpp b/src/amd/compiler/tests/helpers.cpp
index f0ab616d27e..c7df8f2e9fc 100644
--- a/src/amd/compiler/tests/helpers.cpp
+++ b/src/amd/compiler/tests/helpers.cpp
@@ -165,6 +165,25 @@ void finish_opt_test()
    aco_print_program(program.get(), output);
 }
 
+void finish_ra_test(ra_test_policy policy)
+{
+   finish_program(program.get());
+   if (!aco::validate_ir(program.get())) {
+      fail_test("Validation before register allocation failed");
+      return;
+   }
+
+   program->workgroup_size = program->wave_size;
+   aco::live live_vars = aco::live_var_analysis(program.get());
+   aco::register_allocation(program.get(), live_vars.live_out, policy);
+
+   if (aco::validate_ra(program.get())) {
+      fail_test("Validation after register allocation failed");
+      return;
+   }
+   aco_print_program(program.get(), output);
+}
+
 void finish_to_hw_instr_test()
 {
    finish_program(program.get());
diff --git a/src/amd/compiler/tests/helpers.h b/src/amd/compiler/tests/helpers.h
index 3ce9fab3de3..a81de09ff84 100644
--- a/src/amd/compiler/tests/helpers.h
+++ b/src/amd/compiler/tests/helpers.h
@@ -67,6 +67,10 @@ extern aco::Builder bld;
 extern aco::Temp exec_input;
 extern aco::Temp inputs[16];
 
+namespace aco {
+struct ra_test_policy;
+}
+
 void create_program(enum chip_class chip_class, aco::Stage stage,
                     unsigned wave_size=64, enum radeon_family family=CHIP_UNKNOWN);
 bool setup_cs(const char *input_spec, enum chip_class chip_class,
@@ -76,6 +80,7 @@ bool setup_cs(const char *input_spec, enum chip_class chip_class,
 void finish_program(aco::Program *program);
 void finish_validator_test();
 void finish_opt_test();
+void finish_ra_test(aco::ra_test_policy);
 void finish_to_hw_instr_test();
 void finish_assembler_test();
 
diff --git a/src/amd/compiler/tests/meson.build b/src/amd/compiler/tests/meson.build
index 8baad83fe17..712a32ced9b 100644
--- a/src/amd/compiler/tests/meson.build
+++ b/src/amd/compiler/tests/meson.build
@@ -26,6 +26,7 @@ aco_tests_files = files(
   'test_builder.cpp',
   'test_isel.cpp',
   'test_optimizer.cpp',
+  'test_regalloc.cpp',
   'test_to_hw_instr.cpp',
   'test_tests.cpp',
 )
diff --git a/src/amd/compiler/tests/test_regalloc.cpp b/src/amd/compiler/tests/test_regalloc.cpp
new file mode 100644
index 00000000000..ef93f991dab
--- /dev/null
+++ b/src/amd/compiler/tests/test_regalloc.cpp
@@ -0,0 +1,60 @@
+/*
+ * Copyright © 2020 Valve Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+#include "helpers.h"
+
+using namespace aco;
+
+BEGIN_TEST(regalloc.subdword_alloc.reuse_16bit_operands)
+   /* Registers of operands should be "recycled" for the output. But if the
+    * input is smaller than the output, that's not generally possible. The
+    * first v_cvt_f32_f16 instruction below uses the upper 16 bits of v0
+    * while the lower 16 bits are still live, so the output must be stored in
+    * a register other than v0. For the second v_cvt_f32_f16, the original
+    * value stored in v0 is no longer used and hence it's safe to store the
+    * result in v0.
+    */
+
+   for (chip_class cc = GFX8; cc < NUM_GFX_VERSIONS; cc = (chip_class)((unsigned)cc + 1)) {
+      for (bool pessimistic : { false, true }) {
+         const char* subvariant = pessimistic ? "/pessimistic" : "/optimistic";
+
+         //>> v1: %_:v[#a], s2: %_:exec = p_startpgm
+         if (!setup_cs("v1", (chip_class)cc, CHIP_UNKNOWN, subvariant))
+            return;
+
+         //! v2b: %_:v[#a][0:16], v2b: %res1:v[#a][16:32] = p_split_vector %_:v[#a]
+         Builder::Result tmp = bld.pseudo(aco_opcode::p_split_vector, bld.def(v2b), bld.def(v2b), inputs[0]);
+
+         //! v1: %_:v[#b] = v_cvt_f32_f16 %_:v[#a][16:32]
+         //! v1: %_:v[#a] = v_cvt_f32_f16 %_:v[#a][0:16]
+         //; success = (b != a)
+         auto result1 = bld.vop1(aco_opcode::v_cvt_f32_f16, bld.def(v1), tmp.def(1).getTemp());
+         auto result2 = bld.vop1(aco_opcode::v_cvt_f32_f16, bld.def(v1), tmp.def(0).getTemp());
+         writeout(0, result1);
+         writeout(1, result2);
+
+         finish_ra_test(ra_test_policy { pessimistic });
+      }
+   }
+END_TEST



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