Mesa (master): pan/midgard: Fix scheduling issue with csel + render target reference

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Module: Mesa
Branch: master
Commit: 7eaf21cb6f67adbe0e79b80b4feb8c816a98a720
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=7eaf21cb6f67adbe0e79b80b4feb8c816a98a720

Author: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>
Date:   Mon Feb  3 08:19:41 2020 -0500

pan/midgard: Fix scheduling issue with csel + render target reference

Fixes dEQP-GLES3.functional.shaders.fragdepth.write.dynamic_conditional_write

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>
Signed-off-by: Boris Brezillon <boris.brezillon at collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3697>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3697>

---

 src/panfrost/midgard/midgard_schedule.c | 30 ++++++++++++++++++------------
 1 file changed, 18 insertions(+), 12 deletions(-)

diff --git a/src/panfrost/midgard/midgard_schedule.c b/src/panfrost/midgard/midgard_schedule.c
index 1697f086390..84a4281f7ff 100644
--- a/src/panfrost/midgard/midgard_schedule.c
+++ b/src/panfrost/midgard/midgard_schedule.c
@@ -858,6 +858,24 @@ mir_schedule_alu(
                         unreachable("Bad condition");
         }
 
+        /* If we have a render target reference, schedule a move for it. Since
+         * this will be in sadd, we boost this to prevent scheduling csel into
+         * smul */
+
+        if (writeout && (branch->constants.u32[0] || ctx->is_blend)) {
+                sadd = ralloc(ctx, midgard_instruction);
+                *sadd = v_mov(~0, make_compiler_temp(ctx));
+                sadd->unit = UNIT_SADD;
+                sadd->mask = 0x1;
+                sadd->has_inline_constant = true;
+                sadd->inline_constant = branch->constants.u32[0];
+                branch->src[1] = sadd->dest;
+
+                /* Mask off any conditionals. Could be optimized to just scalar
+                 * conditionals TODO */
+                predicate.no_cond = true;
+        }
+
         mir_choose_alu(&smul, instructions, worklist, len, &predicate, UNIT_SMUL);
 
         if (!writeout) {
@@ -913,18 +931,6 @@ mir_schedule_alu(
                         unreachable("Bad condition");
         }
 
-        /* If we have a render target reference, schedule a move for it */
-
-        if (writeout && (branch->constants.u32[0] || ctx->is_blend)) {
-                sadd = ralloc(ctx, midgard_instruction);
-                *sadd = v_mov(~0, make_compiler_temp(ctx));
-                sadd->unit = UNIT_SADD;
-                sadd->mask = 0x1;
-                sadd->has_inline_constant = true;
-                sadd->inline_constant = branch->constants.u32[0];
-                branch->src[1] = sadd->dest;
-        }
-
         /* Stage 2, let's schedule sadd before vmul for writeout */
         mir_choose_alu(&sadd, instructions, worklist, len, &predicate, UNIT_SADD);