Mesa (19.3): 64 new commits
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Thu Feb 13 19:07:54 UTC 2020
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7a3190eb9183c6cb5d24d9a0d4e2be38e91a943d
Author: Dylan Baker <dylan at pnwbakers.com>
Date: Thu Feb 13 11:07:14 2020 -0800
VERSION: bump version for 19.3.4
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=bbb7efcd2faee08ba62aab2d781eb7e25986c581
Author: Dylan Baker <dylan at pnwbakers.com>
Date: Thu Feb 13 11:06:56 2020 -0800
docs: Add release notes for 19.3.4
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=42e7b158a37a6f23b3e5d7b4df68037206b94a16
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Tue Feb 4 17:25:35 2020 +0100
nir: do not use De Morgan's Law rules for flt and fge
In presence of NaNs, "!(flt(a, b) && flt(c, d))" is NOT EQUAL
to "fge(a, b) || fge(c, d)". These optimizations are unsafe for
apps that rely on NaN behaviour.
pipeline-db (GFX9/LLVM):
Totals from affected shaders:
SGPRS: 3176 -> 3136 (-1.26 %)
VGPRS: 2188 -> 2144 (-2.01 %)
Spilled SGPRs: 227 -> 169 (-25.55 %)
Code Size: 150572 -> 151800 (0.82 %) bytes
Max Waves: 307 -> 310 (0.98 %)
pipeline-db (GFX9/ACO):
Totals from affected shaders:
SGPRS: 18744 -> 18744 (0.00 %)
VGPRS: 15576 -> 15580 (0.03 %)
Spilled SGPRs: 164 -> 164 (0.00 %)
Code Size: 1573012 -> 1576492 (0.22 %) bytes
Max Waves: 1534 -> 1532 (-0.13 %)
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2127
Fixes: d1ed4ffe0b7 ("nir: Use De Morgan's Law on logic compounded comparisons")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3696>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3696>
(cherry picked from commit 8e7728077435c5c5ad8c328761277f8ff3b32112)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8f630dc7c5483a75fe8fd890be03586dfa79779b
Author: Eric Anholt <eric at anholt.net>
Date: Wed Feb 5 10:38:57 2020 -0800
Revert "gallium: Fix big-endian addressing of non-bitmask array formats."
This reverts the functional part of commit
d17ff2f7f1864c81c1e00d04baf20f953c6d276a, leaving the unit test for
mesa/pipe agreement on what's an array.
The issue is that the util_channel_desc.shift values on array formats are
not used for bit addressing in memory, they're bit addressing within a
word treating a pixel of the format as a native type, as seen by
llvmpipe's use of the values to do shifts (see
lp_build_unpack_arith_rgba_aos() for example). This means the values are
nonsensical for 3-byte RGB, but then llvmpipe doesn't expose those formats
so it works out.
I still want to clean up our big-endian format handling at some point, but
let's fix the s390x regression first, sort out our format unit tests in
CI, then be able to refactor with confidence.
Fixes: d17ff2f7f186 ("gallium: Fix big-endian addressing of non-bitmask array formats.")
Closes: #2472
Acked-by: Marek Olšák <marek.olsak at amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3721>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3721>
(cherry picked from commit 1886dbfe7362baa221009371434f158b97183164)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=007013c754ac1b0b98e5950b0bc6aaa3d330c3ff
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Jan 30 16:58:15 2020 -0500
radeonsi: fix the DCC MSAA bug workaround
Cc: 19.3 20.0 <mesa-stable at lists.freedesktop.org>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3646>
(cherry picked from commit fbb27eebc8cab1a5d70ea67a37de8d18f20a88f0)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c17c8119c3d8b3a8efb04d74db76337929adea11
Author: Neha Bhende <bhenden at vmware.com>
Date: Mon Feb 10 10:39:51 2020 -0800
svga: fix size of format_conversion_table[]
Since we are now using sparse matrix for format_conversion_table,
we have to make sure we have last entry in table which gives the
sense of required size of format_conversion_table
Fixes: 84db6ba7 ("svga: Drop unsupported formats from the format table")
Reviewed-by: Charmaine Lee <charmainel at vmware.com>
(cherry picked from commit 470e73e7f86b4530cf789a779f43674ecec91881)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=dfcc06cd7a2fcf03fe8a022d47131239cbbec9f1
Author: Dylan Baker <dylan at pnwbakers.com>
Date: Tue Feb 11 09:26:56 2020 -0800
.pick_status.json: Update to 23037627359e739c42b194dec54875aefbb9d00b
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=196a68dfbc3bbb26193f1a7b10c9dbd75338ffbb
Author: Georg Lehmann <dadschoorse at gmail.com>
Date: Thu Feb 6 22:38:35 2020 +0100
Vulkan overlay: use the corresponding image index for each swapchain
pImageIndices should be a pointer to the current image index
otherwise every swapchain but the first one could have a wrong image index
Cc: <mesa-stable at lists.freedesktop.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3741>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3741>
(cherry picked from commit 7283c33b981f975361e3bfa62a339c88f2642cbb)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b23a12725834bb1c82387d9883f4e36f7a3d94fd
Author: Hyunjun Ko <zzoon at igalia.com>
Date: Thu Nov 7 05:28:41 2019 +0000
freedreno/ir3: put the conversion back for half const to the right place.
The previous commit leads to match immed values unexpectedly.
This makes constlen for each shader including bvert wrong.
Also fixes atan2 for mediump deqp tests.
Fixes: cbd1f47433b ("freedreno/ir3: convert back to 32-bit values for half constant registers.")
v2: Move conversion up above fabs/fneg modifier handling as well.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3737>
(cherry picked from commit 260bd32b58a55ac0d9870497caef3a4602e19d47)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=19946a1d2362afa68e685bcea94a3000c2f75079
Author: Dylan Baker <dylan at pnwbakers.com>
Date: Mon Feb 10 09:01:33 2020 -0800
.pick_status.json: Update to 689817c9dfde9a0852f2b2489cb0fa93ffbcb215
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7aacd7dff06c1b5aa574afa796e3baec60b7fab5
Author: Georg Lehmann <dadschoorse at gmail.com>
Date: Thu Feb 6 22:29:42 2020 +0100
Vulkan Overlay: Don't try to change the image layout to present twice
The render pass already does the transition.
The pipeline barrier is still needed to transfer the queue family ownership.
Fixes: 320b0f66c274 ("vulkan/overlay: bounce image back to present layout")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3740>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3740>
(cherry picked from commit f239bb8020df4176ca539bafff327ab5c8da2c2e)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ee4a747ef880a24ce8871acbf88c22e646328212
Author: Georg Lehmann <dadschoorse at gmail.com>
Date: Wed Feb 5 18:06:55 2020 +0000
Correctly wait in the fragment stage until all semaphores are signaled
This fixes two issues:
- a crash if the application uses more than one semaphore for presenting because the driver expects one stage per semaphore
- the swapchain image could be not ready yet if the semaphores aren't signaled, #946 is possible related
Cc: <mesa-stable at lists.freedesktop.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3718>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3718>
(cherry picked from commit 1c79afd94620925cb9e0903f24f91c3ab9ecfcb4)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=632f18ea171c466745b49c34351a6b5bea9e569b
Author: Thomas Hellstrom <thellstrom at vmware.com>
Date: Wed Feb 5 07:54:19 2020 +0100
svga: Fix banded DMA upload
A previous commit ("winsys/svga: Limit the maximum DMA hardware buffer
size") made banded DMA transfer kick in when transfering gnome-shell
window contents under gnome-shell / wayland. This uncovered a bug where
we assumed that banded DMA transfers always occur to the top (y=0) of the
surface.
Fix this by taking the destination y offset into account.
Cc: 19.2 19.3 20.0 <mesa-stable at lists.freedesktop.org>
Fixes: 287c94ea498 ("Squashed commit of the following:")
Signed-off-by: Thomas Hellstrom <thellstrom at vmware.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
Reviewed-by: Charmaine Lee <charmainel at vmware.com>
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3733>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3733>
(cherry picked from commit 451cf228d53ba8f51beb3dcf04370e126fb7ccb6)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=10a0b602b488d76a70f5792749457ee655d1e8a8
Author: Rafael Antognolli <rafael.antognolli at intel.com>
Date: Mon Aug 19 12:28:55 2019 -0700
intel: Load the driver even if I915_PARAM_REVISION is not found.
This param is only available starting on kernel 4.1. Use a default
value of 0 if it is not found instead.
v2: Update commit message (Lionel)
Cc: Jordan Justen <jordan.l.justen at intel.com>
Cc: Mark Janes <mark.a.janes at intel.com>
Fixes: 96e1c945f2b ("i965: Move device info initialization to common
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg at google.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3727>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3727>
(cherry picked from commit 4aa7af9e9a4c19e10afaf4a3c756e62cf4d352c3)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4656d2d30a8c176d81f31827302cd082eff59de3
Author: Vinson Lee <vlee at freedesktop.org>
Date: Sat Feb 1 01:12:32 2020 -0800
swr: Fix GCC 4.9 checks.
Fixes: f0a22956be48 ("swr/rast: _mm*_undefined_* implementations for gcc<4.9")
Fixes: e21fc2c62527 ("swr/rast: non-regex knob fallback code for gcc < 4.9")
Signed-off-by: Vinson Lee <vlee at freedesktop.org>
Reviewed-by: Jan Zielinski <jan.zielinski at intel.com>
(cherry picked from commit deb2bbf57ec1d0660dd85b7080bf5ebeb10e8768)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c2abb8f2709fa7b0ca89b2c0be4dd758597df313
Author: Dylan Baker <dylan at pnwbakers.com>
Date: Fri Feb 7 09:10:22 2020 -0800
.pick_status.json: Update to d8bae10bfe0f487dcaec721743cd51441bcc12f5
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=88aa4b77b7436352193e1e32d4729bb7cafefb78
Author: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
Date: Thu Jan 16 12:31:24 2020 +0100
radeonsi: stop using the VM_ALWAYS_VALID flag
Allocation all the bo as ALWAYS_VALID means they must all fit in memory
(vram + gtt) at each command submission.
This causes some trouble when the total allocated memory is greater than
the available memory.
Possible solutions:
- being able to tag/untag a bo as ALWAYS_VALID: would require kernel changes
- disable VM_ALWAYS_VALID when memory usage is more than a percentage of the
available memory
- disable VM_ALWAYS_VALID entirely
v1 of this patch implemented option 2. v2 (this version) implements option 3.
Related issues:
- https://gitlab.freedesktop.org/drm/amd/issues/607
- https://gitlab.freedesktop.org/mesa/mesa/issues/1257
It also helps with some piglit tests (-t maxsize -t "max[_-].*size" -t maxuniformblocksize):
instead of crashing the machine, the tests fail cleanly.
(cherry-pick from ab54624d0d52d88da7fb7f4df61f33f600a1dfd7)
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3709>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3709>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=03b457e0f2d49ac9f33fa8cd041834599c547412
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Tue Nov 12 13:43:21 2019 +0200
mesa: allow bit queries for EXT_disjoint_timer_query
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2090
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3707>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3707>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a3e4b96ea6dce86a66023202a709031b424052d7
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Tue Nov 19 12:44:29 2019 +0200
mapi: add GetInteger64vEXT with EXT_disjoint_timer_query
From EXT_disjoint_timer_query spec:
"Interaction: This extension adds GetInteger64vEXT if
OpenGL ES 3.0 is not supported"
See https://github.com/KhronosGroup/OpenGL-Registry/issues/326.
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2090
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3707>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6cd88f51f3c758cb77f8cb578cf6a2ee227ca92b
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Wed Jan 22 16:23:14 2020 -0800
intel/fs: Don't count integer instructions as being possibly coissue
Integer instructions don't coissue. Before e64be391dd0
("intel/compiler: generalize the combine constants pass"), this pass
only looked at float sources. There's no shader-db data in that commit,
so I collected some. The results are not good:
Haswell
total instructions in shared programs: 11898805 -> 11908127 (0.08%)
instructions in affected programs: 1218680 -> 1228002 (0.76%)
helped: 2
HURT: 5171
helped stats (abs) min: 12 max: 111 x̄: 61.50 x̃: 61
helped stats (rel) min: 1.59% max: 9.20% x̄: 5.40% x̃: 5.40%
HURT stats (abs) min: 1 max: 311 x̄: 1.83 x̃: 1
HURT stats (rel) min: 0.02% max: 9.91% x̄: 1.05% x̃: 0.70%
95% mean confidence interval for instructions value: 1.55 2.05
95% mean confidence interval for instructions %-change: 1.02% 1.08%
Instructions are HURT.
total cycles in shared programs: 221664974 -> 221404750 (-0.12%)
cycles in affected programs: 120012620 -> 119752396 (-0.22%)
helped: 3464
HURT: 3159
helped stats (abs) min: 1 max: 428160 x̄: 314.55 x̃: 16
helped stats (rel) min: <.01% max: 57.33% x̄: 3.40% x̃: 1.28%
HURT stats (abs) min: 1 max: 87846 x̄: 262.54 x̃: 14
HURT stats (rel) min: <.01% max: 85.57% x̄: 3.01% x̃: 0.77%
95% mean confidence interval for cycles value: -224.23 145.65
95% mean confidence interval for cycles %-change: -0.50% -0.19%
Inconclusive result (value mean confidence interval includes 0).
total spills in shared programs: 9804 -> 10047 (2.48%)
spills in affected programs: 6869 -> 7112 (3.54%)
helped: 2
HURT: 41
total fills in shared programs: 19863 -> 20319 (2.30%)
fills in affected programs: 17428 -> 17884 (2.62%)
helped: 2
HURT: 41
LOST: 20
GAINED: 13
This also prevents regressions in "intel/fs: Promote integer constants
after lowering integer multiplication" (note: that patch will probably
not be committed). When the passes are reorderd, code like
mul(8) acc0<1>D g9<8,8,1>D -2078209981D { align1 1Q };
gets turned into
mov(1) g23<1>D 2078209981D { align1 WE_all 1N };
...
mul(8) acc0<1>D g13<8,8,1>D -g23<0,1,0>D { align1 1Q compacted };
It's not 100% clear why, but these produce different results. Note that
-2078209981 & 0x0ffff = 0x0843, and -(2078209981 & 0x0ffff) =
0xffff0843. It seems like the upper 16-bits of the negation should be
ignored.
Fixes: e64be391dd0 ("intel/compiler: generalize the combine constants pass")
Cc: Iago Toral Quiroga <itoral at igalia.com>
Suggested-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
The shaders with spills or fills hurt are the usual suspects. A couple
compute shaders in Dirt Showdown and a compute shader in Bioshock
Infinite. On Haswell, a compute shader (that appears twice in
shader-db) from Aztec Ruins was also hurt for spill and fills.
Haswell
total instructions in shared programs: 11573934 -> 11568335 (-0.05%)
instructions in affected programs: 828623 -> 823024 (-0.68%)
helped: 2825
HURT: 6
helped stats (abs) min: 1 max: 134 x̄: 2.16 x̃: 1
helped stats (rel) min: 0.02% max: 9.05% x̄: 0.84% x̃: 0.61%
HURT stats (abs) min: 1 max: 216 x̄: 81.83 x̃: 56
HURT stats (rel) min: 0.16% max: 8.65% x̄: 4.21% x̃: 4.68%
95% mean confidence interval for instructions value: -2.31 -1.64
95% mean confidence interval for instructions %-change: -0.85% -0.80%
Instructions are helped.
total cycles in shared programs: 187573593 -> 187004633 (-0.30%)
cycles in affected programs: 82816107 -> 82247147 (-0.69%)
helped: 2186
HURT: 1741
helped stats (abs) min: 1 max: 35230 x̄: 326.96 x̃: 16
helped stats (rel) min: <.01% max: 46.11% x̄: 3.11% x̃: 0.90%
HURT stats (abs) min: 1 max: 6138 x̄: 83.73 x̃: 16
HURT stats (rel) min: <.01% max: 104.11% x̄: 2.73% x̃: 0.75%
95% mean confidence interval for cycles value: -197.13 -92.64
95% mean confidence interval for cycles %-change: -0.72% -0.33%
Cycles are helped.
total spills in shared programs: 7870 -> 7743 (-1.61%)
spills in affected programs: 2260 -> 2133 (-5.62%)
helped: 31
HURT: 5
total fills in shared programs: 6320 -> 6263 (-0.90%)
fills in affected programs: 3547 -> 3490 (-1.61%)
helped: 31
HURT: 6
LOST: 9
GAINED: 9
Ivybridge
total instructions in shared programs: 11863372 -> 11859793 (-0.03%)
instructions in affected programs: 757183 -> 753604 (-0.47%)
helped: 2236
HURT: 3
helped stats (abs) min: 1 max: 81 x̄: 1.86 x̃: 1
helped stats (rel) min: 0.03% max: 5.26% x̄: 0.74% x̃: 0.48%
HURT stats (abs) min: 11 max: 301 x̄: 192.33 x̃: 265
HURT stats (rel) min: 1.55% max: 10.51% x̄: 6.89% x̃: 8.62%
95% mean confidence interval for instructions value: -2.01 -1.18
95% mean confidence interval for instructions %-change: -0.77% -0.70%
Instructions are helped.
total cycles in shared programs: 178377378 -> 177946087 (-0.24%)
cycles in affected programs: 76261390 -> 75830099 (-0.57%)
helped: 1635
HURT: 1395
helped stats (abs) min: 1 max: 34796 x̄: 333.53 x̃: 16
helped stats (rel) min: <.01% max: 47.15% x̄: 2.82% x̃: 0.64%
HURT stats (abs) min: 1 max: 4315 x̄: 81.74 x̃: 18
HURT stats (rel) min: <.01% max: 49.98% x̄: 1.99% x̃: 0.53%
95% mean confidence interval for cycles value: -197.06 -87.62
95% mean confidence interval for cycles %-change: -0.78% -0.43%
Cycles are helped.
total spills in shared programs: 4188 -> 4182 (-0.14%)
spills in affected programs: 1557 -> 1551 (-0.39%)
helped: 30
HURT: 3
total fills in shared programs: 5056 -> 5245 (3.74%)
fills in affected programs: 2708 -> 2897 (6.98%)
helped: 30
HURT: 3
LOST: 5
GAINED: 1
No shader-db changes on any other Intel platform.
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3544>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3544>
(cherry picked from commit 59488cbbaca1268841fe5ba42d0a1202b33be23b)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5e7ee64037f699204bddecaf0d6021b81c78ef0c
Author: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Date: Thu Jan 30 17:58:55 2020 +0100
radv: Do not set SX DISABLE bits for RB+ with unused surfaces.
The extra bits in CB_SHADER_MASK break dual source blending in
SkQP on a Stoney device. However:
- As far as I can tell, some other dual source blend tests are passing
before and after the change.
- A hacked around skqp passes on my Vega desktop and Raven laptop
- Getting Skqp to give any useful info or to run it outside of Android
on ChromeOS is proving difficult.
I have confirmed 3 strategies that seem to work:
- The old radv behavior of setting CB_SHADER_MASK to 0xF
- AMDVLK: CB_SHADER_MASK = 0xFF, and the 3 RB+ regs
are 0.
- radeonsi: CB_SHADER_MASK = 0xFF, but does not set DISABLE
bits in SX_BLEND_OPT_CONTROL for CB 1-7.
Let us use the radeonsi solution as that solution also seems like the correct
thing to do for holes. I have tested on my Raven laptop that setting the high
surfaces to not disabled and downconvert to 32_R does not imply a performance
penalty.
Fixes: e9316fdfd48 "radv: fix setting CB_SHADER_MASK for dual source blending"
Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3670>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3670>
(cherry picked from commit 65a6dc5139fddd5e01eaedcc57fc67e0a6a28c94)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6dd380da0ce4244c5e6f16e085423cd69101373d
Author: Danylo Piliaiev <danylo.piliaiev at globallogic.com>
Date: Fri Dec 27 15:12:24 2019 +0200
st/mesa: Handle the rest renderbuffer formats from OSMesa
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2189
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/989
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2036
CC: <mesa-stable at lists.freedesktop.org>
Signed-off-by: Danylo Piliaiev <danylo.piliaiev at globallogic.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3216>
(cherry picked from commit d83abf1d378be059b4f41a6a44a9bf24c7394084)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e1579d961341c3601a52fbb7403df43ac797ec12
Author: Danylo Piliaiev <danylo.piliaiev at globallogic.com>
Date: Wed Jan 29 14:34:50 2020 +0200
i965: Do not set front_buffer_dirty if there is no front buffer
Otherwise there will be a warning:
"libEGL warning: FIXME: egl/x11 doesn't support front buffer rendering."
Happens with EGL_KHR_surfaceless_context:
eglMakeCurrent(egl_display, EGL_NO_SURFACE, EGL_NO_SURFACE, egl_context)
eglMakeCurrent(egl_display, egl_surface, egl_surface, egl_context)
glFlush() // Here will be a warning
Cc: <mesa-stable at lists.freedesktop.org>
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1525
Signed-off-by: Danylo Piliaiev <danylo.piliaiev at globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3628>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3628>
(cherry picked from commit 36126b6211f1ac2da0aa94411608b2320553dbb6)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=88865d41f1065023523bbda237172bf38597a4fd
Author: Dylan Baker <dylan at pnwbakers.com>
Date: Wed Feb 5 08:52:21 2020 -0800
.pick_status.json: Mark ca6a22305b275b49fbc88b8f4cba2fefb24c2a5d as backported
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7f2c7e09b97edaa48c3e35835ef2058bbeba9001
Author: Dylan Baker <dylan at pnwbakers.com>
Date: Wed Feb 5 08:52:09 2020 -0800
.pick_status.json: Update to 7eaf21cb6f67adbe0e79b80b4feb8c816a98a720
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ee2a8992f08ba99c616bb3a90377864e95692144
Author: Michel Dänzer <mdaenzer at redhat.com>
Date: Fri Jan 31 18:24:31 2020 +0100
winsys/amdgpu: Close KMS handles for other DRM file descriptions
When a BO or amdgpu_screen_winsys is destroyed.
Should fix leaking such BOs in other DRM file descriptions.
v2:
* Pass the correct file descriptor to drmIoctl (Pierre-Eric
Pelloux-Prayer)
* Use _mesa_hash_table_remove
v3:
* Close handles in amdgpu_winsys_unref as well
v4:
* Adapt to amdgpu_winsys::sws_list_lock.
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2270
Fixes: 11a3679e3aba "winsys/amdgpu: Make KMS handles valid for original
DRM file descriptor"
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
(Cherry picked from commit ca6a22305b275b49fbc88b8f4cba2fefb24c2a5d)
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3693>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3693>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b8a7b7efd98878408dcabfcde8cd91de172cc664
Author: Michel Dänzer <mdaenzer at redhat.com>
Date: Fri Jan 31 18:22:14 2020 +0100
winsys/amdgpu: Re-use amdgpu_screen_winsys when possible
Namely, if os_same_file_description determined that the DRM file
descriptor references the same file description.
v2:
* Adapt to amdgpu_winsys::sws_list_lock.
v3:
* Fix comparison of amdgpu_screen_winsys file descriptions, see
https://gitlab.freedesktop.org/mesa/mesa/issues/2413 .
* Lock amdgpu_winsys::sws_list_lock for traversing the sws_list in
amdgpu_winsys_create.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
(Cherry picked from commit 9f2bed49d476a15af0df270307f9051d810ea0ab)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3693>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ed271a9c2f40f8ec881bf3e4568d35dbfcd9cf70
Author: Michel Dänzer <mdaenzer at redhat.com>
Date: Fri Jan 31 18:22:48 2020 +0100
util: Add os_same_file_description helper
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
(Cherry picked from commit f76cbc7901f7d500f5a4f74aedfd29970d1efd00)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3693>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b8db24315a302118ee9da060b2ef360f6622bf0c
Author: Michel Dänzer <mdaenzer at redhat.com>
Date: Fri Jan 31 18:21:42 2020 +0100
winsys/amdgpu: Only re-export KMS handles for different DRM FDs
When the amdgpu_screen_winsys uses the same FD as the amdgpu_winsys
(which is always the case for the first amdgpu_screen_winsys), we can
just use bo->u.real.kms_handle.
v2:
* Also only create the kms_handles hash table if the
amdgpu_screen_winsys fd is different from the amdgpu_winsys one.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
(Cherry picked from commit c6468f66c7a47f0e16df2f1200db33eef6d2d1f4)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3693>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=159995be353533d4ac7f59c9bb0f4edbd7c3741e
Author: Michel Dänzer <mdaenzer at redhat.com>
Date: Fri Jan 31 18:21:08 2020 +0100
winsys/amdgpu: Keep track of retrieved KMS handles using hash tables
The assumption being that KMS handles are only retrieved for relatively
few BOs, so hash tables should be efficient both in terms of performance
and memory consumption.
We use the address of struct amdgpu_winsys_bo as the key and its
kms_handle field (the KMS handle valid for the DRM file descriptor
passed to amdgpu_device_initialize) as the hash value.
v2:
* Add comment above amdgpu_screen_winsys::kms_handles (Pierre-Eric
Pelloux-Prayer)
v3:
* Protect kms_handles hash table with amdgpu_winsys::sws_list_lock
mutex.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
(Cherry picked from commit 24075ac60fcc09dad173cb792e8f186c6379c086)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3693>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=23900be9109e6653536ccf52e3a9b14565478346
Author: Michel Dänzer <mdaenzer at redhat.com>
Date: Fri Jan 31 18:20:08 2020 +0100
winsys/amdgpu: Keep a list of amdgpu_screen_winsyses in amdgpu_winsys
v2:
* Add dedicated mutex for the list.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
(Cherry picked from commit f4010a6da9720b1593ca34faf0d8722ca85ed6c2)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3693>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=88986b59f3185c04a68f331942a45e64c46913d6
Author: Marek Vasut <marex at denx.de>
Date: Thu Jan 30 01:40:31 2020 +0100
etnaviv: Destroy rsc->pending_ctx set in etna_resource_destroy()
Destroy rsc->pending_ctx set in etna_resource_destroy(), otherwise
the memory is allocated, never free'd, and becomes unreachable. This
fixes a memory leak.
Fixes: 9e672e4d20fb ("etnaviv: keep references to pending resources")
Cc: <mesa-stable at lists.freedesktop.org>
Signed-off-by: Marek Vasut <marex at denx.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner at gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3633>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3633>
(cherry picked from commit c32bd325e7688c781b7e5de58a2d0534c82f00a0)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d78f3577e6b57c7a6bce0d621240dd3bf6edf663
Author: Jan Vesely <jan.vesely at rutgers.edu>
Date: Thu Jan 30 01:23:54 2020 -0500
clover: Use explicit conversion from llvm::StringRef to std::string
Fixes build after llvm 777180a32b61070a10dd330b4f038bf24e916af1
("[ADT] Make StringRef's std::string conversion operator explicit")
CC: <mesa-stable at lists.freedesktop.org>
Signed-off-by: Jan Vesely <jan.vesely at rutgers.edu>
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
(cherry picked from commit 0ccda2ebff83816cecf4dcb48f367a0d5c8f5fb1)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7c5f6dd0efbeb220ac1bdd37638b2349922cfdd4
Author: Dylan Baker <dylan at pnwbakers.com>
Date: Tue Feb 4 08:08:14 2020 -0800
.pick_status.json: Update to 9afdcd64f2c96f3fcc1a28912987f2e8066aa995
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1aee273e3b8acf59151c236ad367642662f6c9f9
Author: Boris Brezillon <boris.brezillon at collabora.com>
Date: Fri Jan 31 13:42:19 2020 +0100
panfrost: Fix the damage box clamping logic
When the rendering are is not covering the whole FBO, and the biggest
damage rect is empty, we can have damage.max{x,y} > damage.min{x,y},
which leads to invalid reload boxes.
Fixes: 65ae86b85422 ("panfrost: Add support for KHR_partial_update()")
Signed-off-by: Boris Brezillon <boris.brezillon at collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3676>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3676>
(cherry picked from commit b550b7ef3b8d12f533b67b1a03159a127a3ff34a)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6b3c119c508a100c86abe057de8b9d39c62aa281
Author: Jason Ekstrand <jason at jlekstrand.net>
Date: Fri Jan 31 16:08:31 2020 -0600
anv/blorp: Use the correct size for vkCmdCopyBufferToImage
Now that we're using an uncompressed format for the buffer, we have to
scale down the dimensions we pass into BLORP when doing buffer->image
copies.
Fixes: dd92179a72 "anv: Canonicalize buffer formats for image/buffer..."
Closes: #2452
Reviewed-by: Erik Faye-Lund <erik.faye-lund at collabora.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3664>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3664>
(cherry picked from commit d7fe9af6202413aa4e6f0f53d89577ed8ea80027)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6257f10d038a31e11c4c72780272e0b6dbc0b5e8
Author: Jason Ekstrand <jason at jlekstrand.net>
Date: Thu Jan 30 11:34:51 2020 -0600
intel/fs: Write the address register with NoMask for MOV_INDIRECT
This fixes a hang in the following Vulkan CTS test on TGL-LP:
dEQP-VK.descriptor_indexing.storage_buffer_dynamic_in_loop
Cc: mesa-stable at lists.freedesktop.org
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3642>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3642>
(cherry picked from commit f93dfb509cbf9474befae9919dd8c135bbd67093)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1e23188e7b53d69e0deb315f83ef64aada152c80
Author: Jason Ekstrand <jason at jlekstrand.net>
Date: Thu Jan 16 17:54:49 2020 -0600
genxml: Add a new 3DSTATE_SF field on gen12
Cc: mesa-stable at lists.freedesktop.org
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3454>
(cherry picked from commit 9da9abf8a7a605cc9b79bd4240ff715b79ac774a)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=30472cca00e3da02f4b624f893e71d33cce06637
Author: Jason Ekstrand <jason at jlekstrand.net>
Date: Thu Jan 16 17:59:43 2020 -0600
anv,iris: Set 3DSTATE_SF::DerefBlockSize to per-poly on Gen12+
According to the BSpec, this should prevent hangs when using shaders
with large URB entries. A more precise fix can be done but it requires
re-arranging URB setup.
Cc: mesa-stable at lists.freedesktop.org
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3454>
(cherry picked from commit e1bdb127b6875df602bd736465d597725f326621)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9fc714c5ec12e4f9095fac6df053b9f7d48c3a82
Author: Dylan Baker <dylan at pnwbakers.com>
Date: Mon Feb 3 08:32:59 2020 -0800
.pick_status.json: Update to b550b7ef3b8d12f533b67b1a03159a127a3ff34a
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=212ea9260d621f3cc3478636bf9ad05febffa6c2
Author: Dylan Baker <dylan at pnwbakers.com>
Date: Wed Oct 16 11:32:49 2019 -0700
bin/pick-ui: Add a new maintainer script for picking patches
In the long term the goal of this script is to nearly completely
automate the process of picking stable nominations, in a well tested
way.
In the short term the goal is to provide a better, faster UI to interact
with stable nominations.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7f7ceb368f2e5294aad73625c09503fea7dcbb43
Author: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
Date: Fri Jan 17 09:37:57 2020 +0100
radeonsi: disable display DCC
Display DCC needs https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2836
to work correctly.
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3440>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3440>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=23f23f23cbcfbd7f1e9dfbf81424ee0cbb5e058b
Author: Jason Ekstrand <jason at jlekstrand.net>
Date: Wed Jan 22 22:37:10 2020 -0600
anv: Improve BTI change cache flushing
This commit makes two changes:
1. We set pending_pipe_bits instead of emitting PIPE_CONTROL directly
for the flush at the end of cmd_buffer_begin_subpass.
2. Because BLORP ops such as vkCmdClearAttachments may come in the
middle of a render pass, we have to also flag the need for a cache
flush after the blorp op.
Fixes: 185630c6bc97 "anv/blorp: Do the gen11 BTI flush"
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3547>
(cherry picked from commit c70a786c77370bbc47f71a9f529d50116fd511da)
Conflicts:
src/intel/vulkan/genX_cmd_buffer.c
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d6868058763c4bbbf5ade6cb878f4e39445ac63a
Author: Rhys Perry <pendingchaos02 at gmail.com>
Date: Thu Jan 2 15:36:49 2020 +0000
aco: fix target calculation when vgpr spilling introduces sgpr spilling
A shader might require vgpr spilling but not require sgpr spilling. In
that case, the spiller lowers the sgpr target by 5 which could mean sgpr
spilling is then required. Then the vgpr target has to be lowered to make
space for the linear vgprs. Previously, space wasn't make for the linear
vgprs.
Found while testing the spiller on the pipeline-db with a lowered limit
Fixes: a7ff1bb5b9a78cf57073b5e2e136daf0c85078d6
('aco: simplify calculation of target register pressure when spilling')
Signed-off-by: Rhys Perry <pendingchaos02 at gmail.com>
Reviewed-by: Daniel Schürmann <daniel at schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3257>
(cherry picked from commit 590c26beab153fbc7c2193ce65a9a63329a80be8)
Conflicts:
src/amd/compiler/aco_spill.cpp
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9d9c92b8a608c5ca8cd84e3d459a2f63d1f83deb
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Jan 29 00:22:02 2020 -0800
i965: Use brw_batch_references in tex_busy check
If the batch references the buffer, we will have to flush the batch
immediately before mapping it, at which point it will be busy.
(This bug has existed for a long time...even going back to BLT-era...)
Fixes: 779923194c6 ("i965/tex_image: Use meta for instead of the blitter PBO TexImage and GetTexImage")
Fixes: d5d4ba9139a ("i965/tex_subimage: use meta instead of the blitter for PBO TexSubImage")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3616>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3616>
(cherry picked from commit bdba744d700717a123232cf24647f11918fc0dcd)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ce0bea311bac2d44e6e99fdc9c1e0bd7be7f8da1
Author: Rhys Perry <pendingchaos02 at gmail.com>
Date: Tue Jan 7 19:13:08 2020 +0000
aco: don't always add logical edges from continue_break blocks to headers
Otherwise, code like this will be broken:
loop {
if (...) {
break;
} else {
break;
}
}
The continue_or_break block doesn't have any logical predecessors but it's
a logical predecessor of the header block. This liveness error breaks the
spiller in init_live_in_vars() (under "keep variables spilled on all
incoming paths") and eventually creates garbage reloads.
Fixes: 93c8ebfa ('aco: Initial commit of independent AMD compiler')
Signed-off-by: Rhys Perry <pendingchaos02 at gmail.com>
Reviewed-by: Daniel Schürmann <daniel at schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3257>
(cherry picked from commit d282a292eca05bd9f701d8509d674e4697f510ec)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=56bc3836ba14014ac5fbcf2c4c2d244c62d426d8
Author: Rhys Perry <pendingchaos02 at gmail.com>
Date: Thu Jan 2 14:54:31 2020 +0000
aco: don't consider loop header blocks branch blocks in add_coupling_code
Loops without continues create header blocks with only 1 predecessor.
CC: <mesa-stable at lists.freedesktop.org>
Signed-off-by: Rhys Perry <pendingchaos02 at gmail.com>
Reviewed-by: Daniel Schürmann <daniel at schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3257>
(cherry picked from commit 521525fc0a3b9008e70841542ad6e3db4b1ea4d6)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f5f8b1162933043ba57f61d20823e1c7a9e5a655
Author: Dylan Baker <dylan at pnwbakers.com>
Date: Thu Jan 30 10:26:54 2020 -0800
.pick_status.json: Update to f09c466732e4a5b648d7503787777c926dd93c29
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=660e887403f3bf1568ec4461a6aa8c929176d1a5
Author: Dylan Baker <dylan at pnwbakers.com>
Date: Wed Jan 29 09:09:59 2020 -0800
.pick_status.json: Mark 552028c013cc1d49a2b61ebe0fc3a3781a9ba826 as denominated
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=40d3eeb0e34c0089b25495d114761310a5dc6e9f
Author: Rhys Perry <pendingchaos02 at gmail.com>
Date: Mon Jan 13 14:53:56 2020 +0000
aco: run p_wqm instructions in WQM
If the p_wqm ends up creating copies, these need to be in WQM. Helps (but
doesn't completely fix) artifacts in Strange Brigade. The actual issue
still exists and is harder to fix.
Signed-off-by: Rhys Perry <pendingchaos02 at gmail.com>
Fixes: 93c8ebfa780 ('aco: Initial commit of independent AMD compiler')
Reviewed-by: Daniel Schürmann <daniel at schuermann.dev>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3273>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3273>
(cherry picked from commit 404818dd288de1b374c3b5f3589450c382bad3c4)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f7e405bf7cbfd2f3ff8f75d91a82d2371f70d100
Author: Rhys Perry <pendingchaos02 at gmail.com>
Date: Thu Jan 2 19:13:53 2020 +0000
aco: ensure predecessors' p_logical_end is in WQM when a p_phi is in WQM
We want any copies to be in WQM. I don't know if this fixes any real
application, but I can create a vkrunner test than reproduces the issue.
Signed-off-by: Rhys Perry <pendingchaos02 at gmail.com>
Fixes: 93c8ebfa780 ('aco: Initial commit of independent AMD compiler')
Reviewed-by: Daniel Schürmann <daniel at schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3273>
(cherry picked from commit 2d7386a2d037497656aa9c601091fc4dd6d3ced2)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ac3d12717a54bc8195864aa3e35bcdc8035fe756
Author: Dylan Baker <dylan at pnwbakers.com>
Date: Wed Jan 29 09:08:14 2020 -0800
.pick_status.json: Update to ca6a22305b275b49fbc88b8f4cba2fefb24c2a5d
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a350a802cd776be12fb0d39315fc77507902dc53
Author: Drew Davenport <ddavenport at chromium.org>
Date: Mon Jan 27 11:13:19 2020 -0700
radeonsi: Clear uninitialized variable
|view| was not initialized leading to flaky test failures in SkQP
test unitTest_ES2BlendWithNoTexture.
Fixes: 029bfa3d253 "radeonsi: add ability to bind images as image buffers"
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3592>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3592>
(cherry picked from commit 0d99ff54cc3fb1dd85044f8971f6686138a5f149)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e0a3fa8bb283bd325f8523322a4f4e27a5a13c5c
Author: Brian Ho <brian at brkho.com>
Date: Sun Jan 26 19:50:42 2020 -0800
anv: Handle unavailable queries in vkCmdCopyQueryPoolResults
If VK_QUERY_RESULT_WAIT_BIT is not set, there is currently no
special handling of unavailable queries in vkCmdCopyQueryPoolResults,
and anv will write an invalid value for the query result.
This commit updates vkCmdCopyQueryPoolResults for unavailable
queries to return 0 if the VK_QUERY_RESULT_PARTIAL_BIT flag is set
and if not, skip writing altogether.
Cc: <mesa-stable at lists.freedesktop.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3586>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3586>
(cherry picked from commit 815a603889b812edc94bed61a260c76c264a8b9d)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d203c0add7efaca44544ffb463ef0dc73b13baab
Author: Brian Ho <brian at brkho.com>
Date: Sun Jan 26 15:12:11 2020 -0800
anv: Properly fetch partial results in vkGetQueryPoolResults
Currently, fetching the partial results (VK_QUERY_RESULT_PARTIAL_BIT)
of an unavailable occlusion query via vkGetQueryPoolResults can
return invalid values. anv returns slot.end - slot.begin, but in the
case of unavailable queries, slot.end is still at the initial value
of 0. If slot.begin is non-zero, the occlusion count underflows to
a value that is likely outside the acceptable range of the partial
result.
This commit fixes vkGetQueryPoolResults by always returning 0 if the
query is unavailable and the VK_QUERY_RESULT_PARTIAL_BIT is set.
Cc: <mesa-stable at lists.freedesktop.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3586>
(cherry picked from commit af92ce50a7e56d313f5623136d3f09e7c76475fa)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f585257cb0367fccd42a544a149b793be4b03210
Author: Vasily Khoruzhick <anarsoul at gmail.com>
Date: Sat Jan 25 11:40:37 2020 -0800
lima: ppir: don't delete root ld_tex nodes without successors in current block
We don't clone ld_tex nodes into each block anymore, so ld_tex may have
successors in another block.
Fixes: c8554f849e41 ("lima/ppir: don't clone texture loads")
Reviewed-by: Erico Nunes <nunes.erico at gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul at gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3564>
(cherry picked from commit 4a0f62f1fcab5350d6173c843fd95089953431a0)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9250fb9f0e4f14aeb86c54eeea20dab5d43ee4ea
Author: Jason Ekstrand <jason at jlekstrand.net>
Date: Wed Jan 22 14:26:24 2020 -0600
anv: Insert holes for non-existant XFB varyings
Thanks to optimizations, it's possible for varyings to get deleted but
still leave the variable there for nir_gather_xfb_info to find. If we
get into this case, insert a hole.
Fixes: 36ee2fd61c8 "anv: Implement the basic form of..."
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3520>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3520>
(cherry picked from commit 993f866d2e31c06462b49d760debf64d14e54a68)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4ab4ab0b2735fe38a61a71aff1f54352016e49e9
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Mon Jan 27 15:17:25 2020 +0100
radv: do not allow sparse resources with multi-planar formats
It's unsupported.
Fixes some fails or hangs with
dEQP-VK.sparse_resources.image_sparse_binding.*
Cc: 19.3 <mesa-stable at lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3581>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3581>
(cherry picked from commit 83e1fa87a7e25b8e60f0817b09df8b54cfc38abd)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d7bcec9a6c433b12f2a1933955e292313b693760
Author: Rhys Perry <pendingchaos02 at gmail.com>
Date: Thu Jan 23 19:34:06 2020 +0000
aco: fix operand to scc when selecting SGPR ufind_msb/ifind_msb
Signed-off-by: Rhys Perry <pendingchaos02 at gmail.com>
Fixes: 93c8ebfa78 ('aco: Initial commit of independent AMD compiler')
Reviewed-by: Daniel Schürmann <daniel at schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3541>
(cherry picked from commit 92970adb4ba4e64422f46893642f8b85f4e130f5)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b3b73643cac771a3edffd3afbbe32c70def44aa9
Author: Florian Will <florian.will at gmail.com>
Date: Mon Jan 27 10:30:21 2020 +0100
radv/winsys: set IB flags prior to submit in the sysmem path
This fixes missing scene objects in ZUSI 3 + dxvk. Index / vertex buffer
upload using thousands of CopyBuffer commands in one huge Vulkan command
buffer, mixed with lots of render pass begin/end and draw calls, failed
for some of the buffers.
radv divides the huge command buffer into 3 IBs, and they had random
flags set because the field was uninitialized. Maybe IBs got discarded
if they had the PREAMBLE bit set.
Signed-off-by: Florian Will <florian.will at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Cc: <mesa-stable at lists.freedesktop.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3577>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3577>
(cherry picked from commit 951083768b351b0700bdcc02758670e505cce974)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e88a9cc1c07d16d0572f103912777b441489ed34
Author: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Date: Fri Jan 24 15:34:36 2020 +0200
isl: drop CCS row pitch requirement for linear surfaces
We were applying row pitch constraint of CCS surfaces to linear
surfaces. But CCS is only supported in linear tiling under some
condition (more on that in the following commit). So let's drop that
requirement for now.
Fixes a bunch of crucible assert where the byte size of a linear image
is expected to be similar to the byte size of buffer for the same
extent in the following category :
func.miptree.r8g8b8a8-unorm.aspect-color.view-2d.*download-copy-with-draw.*
v2: Move restriction to isl_calc_tiled_min_row_pitch()
v3: Move restrinction to isl_calc_row_pitch_alignment() (Jason)
v4: Update message (Lionel)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Fixes: 07e16221d975 ("isl: Round up some pitches to 512B for Gen12's CCS")
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3551>
(cherry picked from commit a3f6db2c4e927be7e7d40cbc39c8664030d2af59)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=37c25ea299920d7572d2f758c205bd1e516ca0a2
Author: Dylan Baker <dylan at pnwbakers.com>
Date: Tue Jan 28 15:29:25 2020 -0800
.pick_status.json: Update to 997040e4b8353fe9b71a5e9fde2f933eae09c7a3
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f72036c3c7ea79aad59a8a0d7a37d4adc176ece5
Author: Dylan Baker <dylan at pnwbakers.com>
Date: Fri Jan 24 10:43:55 2020 -0800
.pick_status.json: Mark df34fa14bb872447fed9076e06ffc504d85e2d1c as backported
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=bca77e3b99301b7fcbcffbc969c3bbd2cc818a96
Author: Dylan Baker <dylan at pnwbakers.com>
Date: Fri Jan 24 10:43:54 2020 -0800
.pick_status.json: Mark 58c929be0ddbbd9291d0dadbf11538170178e791 as backported
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