Mesa (master): intel/fs: Return consistent UW types from sample_mask_reg() in fragment shaders.

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Module: Mesa
Branch: master
Commit: 04c7d3d4b19610cae8250102fefd0012b7233d9e
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=04c7d3d4b19610cae8250102fefd0012b7233d9e

Author: Francisco Jerez <currojerez at riseup.net>
Date:   Sat Jan  4 16:11:23 2020 -0800

intel/fs: Return consistent UW types from sample_mask_reg() in fragment shaders.

In SIMD32 programs that don't use discard, the upper 16 bits of the UD
result of sample_mask_reg() don't contain the sample mask of the upper
16 channels as one would expect.  Stop pretending we are returning a
valid 32-bit mask.

Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

---

 src/intel/compiler/brw_fs.cpp | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index b19d9b3e8cb..963d1c18155 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -4290,7 +4290,7 @@ sample_mask_reg(const fs_builder &bld)
    } else {
       assert(v->devinfo->gen >= 6 && bld.dispatch_width() <= 16);
       return retype(brw_vec1_grf((bld.group() >= 16 ? 2 : 1), 7),
-                    BRW_REGISTER_TYPE_UD);
+                    BRW_REGISTER_TYPE_UW);
    }
 }
 
@@ -5337,8 +5337,7 @@ emit_predicate_on_sample_mask(const fs_builder &bld, fs_inst *inst)
                 subreg + inst->group / 16).subnr);
    } else {
       bld.group(1, 0).exec_all()
-         .MOV(brw_flag_subreg(subreg + inst->group / 16),
-              retype(sample_mask, BRW_REGISTER_TYPE_UW));
+         .MOV(brw_flag_subreg(subreg + inst->group / 16), sample_mask);
    }
 
    if (inst->predicate) {