Mesa (staging/20.0): i965: Do not generate D16 B5G6R5_UNORM configs on gen < 8
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Thu Feb 20 21:35:52 UTC 2020
Module: Mesa
Branch: staging/20.0
Commit: 5a7ae6be76b9681fbbc71249b6e73ce9c80fe456
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5a7ae6be76b9681fbbc71249b6e73ce9c80fe456
Author: Danylo Piliaiev <danylo.piliaiev at globallogic.com>
Date: Tue Dec 24 14:19:24 2019 +0200
i965: Do not generate D16 B5G6R5_UNORM configs on gen < 8
We don't support MESA_FORMAT_Z_UNORM16 before Gen8, see
intel_screen_init_surface_formats.
As a consequence disables B5G6R5_UNORM configs with depth
on gen < 6.
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2275
CC: <mesa-stable at lists.freedesktop.org>
Signed-off-by: Danylo Piliaiev <danylo.piliaiev at globallogic.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3206>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3206>
(cherry picked from commit 5bfd363be4c957c1f7b5c1f3069346f2bce2cd5a)
---
.pick_status.json | 2 +-
src/mesa/drivers/dri/i965/intel_screen.c | 34 +++++++++++++++++++++-----------
2 files changed, 24 insertions(+), 12 deletions(-)
diff --git a/.pick_status.json b/.pick_status.json
index 3dc0c2cbb89..7eb623f6c0b 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -40,7 +40,7 @@
"description": "i965: Do not generate D16 B5G6R5_UNORM configs on gen < 8",
"nominated": true,
"nomination_type": 0,
- "resolution": 0,
+ "resolution": 1,
"master_sha": null,
"because_sha": null
},
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c
index 7bb2e195d62..0bf2181dc8d 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -2281,7 +2281,7 @@ intel_screen_make_configs(__DRIscreen *dri_screen)
*/
for (unsigned i = 0; i < num_formats; i++) {
__DRIconfig **new_configs;
- int num_depth_stencil_bits = 2;
+ int num_depth_stencil_bits = 1;
if (!intel_allowed_format(dri_screen, formats[i]))
continue;
@@ -2294,16 +2294,20 @@ intel_screen_make_configs(__DRIscreen *dri_screen)
stencil_bits[0] = 0;
if (formats[i] == MESA_FORMAT_B5G6R5_UNORM) {
- depth_bits[1] = 16;
- stencil_bits[1] = 0;
+ if (devinfo->gen >= 8) {
+ depth_bits[num_depth_stencil_bits] = 16;
+ stencil_bits[num_depth_stencil_bits] = 0;
+ num_depth_stencil_bits++;
+ }
if (devinfo->gen >= 6) {
- depth_bits[2] = 24;
- stencil_bits[2] = 8;
- num_depth_stencil_bits = 3;
+ depth_bits[num_depth_stencil_bits] = 24;
+ stencil_bits[num_depth_stencil_bits] = 8;
+ num_depth_stencil_bits++;
}
} else {
- depth_bits[1] = 24;
- stencil_bits[1] = 8;
+ depth_bits[num_depth_stencil_bits] = 24;
+ stencil_bits[num_depth_stencil_bits] = 8;
+ num_depth_stencil_bits++;
}
new_configs = driCreateConfigs(formats[i],
@@ -2327,8 +2331,16 @@ intel_screen_make_configs(__DRIscreen *dri_screen)
continue;
if (formats[i] == MESA_FORMAT_B5G6R5_UNORM) {
- depth_bits[0] = 16;
- stencil_bits[0] = 0;
+ if (devinfo->gen >= 8) {
+ depth_bits[0] = 16;
+ stencil_bits[0] = 0;
+ } else if (devinfo->gen >= 6) {
+ depth_bits[0] = 24;
+ stencil_bits[0] = 8;
+ } else {
+ depth_bits[0] = 0;
+ stencil_bits[0] = 0;
+ }
} else {
depth_bits[0] = 24;
stencil_bits[0] = 8;
@@ -2370,7 +2382,7 @@ intel_screen_make_configs(__DRIscreen *dri_screen)
depth_bits[0] = 0;
stencil_bits[0] = 0;
- if (formats[i] == MESA_FORMAT_B5G6R5_UNORM) {
+ if (formats[i] == MESA_FORMAT_B5G6R5_UNORM && devinfo->gen >= 8) {
depth_bits[1] = 16;
stencil_bits[1] = 0;
} else {
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