Mesa (staging/19.3): intel/gen12: Take into account opcode when decoding SWSB

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Module: Mesa
Branch: staging/19.3
Commit: 6d93c67532338f184ba60d6ae1d2dee7c5b338f0
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=6d93c67532338f184ba60d6ae1d2dee7c5b338f0

Author: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
Date:   Fri Jan 31 10:20:25 2020 -0800

intel/gen12: Take into account opcode when decoding SWSB

The interpretation of the fields is different depending whether the
instruction is a SEND/MATH or not.

This fixes the disassembly output for non-SEND/MATH instructions that
have both in-order and out-of-order dependencies.  Their dependencies
were wrongly represented as `@A $B` when the correct would be `@A
$B.dst`.

Fixes: 6154cdf924f ("intel/eu/gen12: Add auxiliary type to represent SWSB information during codegen.")
Fixes: 83612c01271 ("intel/disasm/gen12: Disassemble software scoreboard information.")
Acked-by: Francisco Jerez <currojerez at riseup.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3660>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3660>
(cherry picked from commit 79788b8f7f07460af8467931501380e47b485e36)

---

 .pick_status.json                   | 2 +-
 src/intel/compiler/brw_disasm.c     | 3 ++-
 src/intel/compiler/brw_eu_defines.h | 7 +++++--
 3 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/.pick_status.json b/.pick_status.json
index 3021aa052d8..3f176a18ba9 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -517,7 +517,7 @@
         "description": "intel/gen12: Take into account opcode when decoding SWSB",
         "nominated": true,
         "nomination_type": 1,
-        "resolution": 0,
+        "resolution": 1,
         "master_sha": null,
         "because_sha": "6154cdf924f4d0d3a6fb0cef38bc62eb4494c69c"
     },
diff --git a/src/intel/compiler/brw_disasm.c b/src/intel/compiler/brw_disasm.c
index 7d821dbc1fa..d0960dbb181 100644
--- a/src/intel/compiler/brw_disasm.c
+++ b/src/intel/compiler/brw_disasm.c
@@ -1607,7 +1607,8 @@ qtr_ctrl(FILE *file, const struct gen_device_info *devinfo, const brw_inst *inst
 static int
 swsb(FILE *file, const struct gen_device_info *devinfo, const brw_inst *inst)
 {
-   const struct tgl_swsb swsb = tgl_swsb_decode(brw_inst_swsb(devinfo, inst));
+   const struct tgl_swsb swsb = tgl_swsb_decode(brw_inst_opcode(devinfo, inst),
+                                                brw_inst_swsb(devinfo, inst));
    if (swsb.regdist)
       format(file, " @%d", swsb.regdist);
    if (swsb.mode)
diff --git a/src/intel/compiler/brw_eu_defines.h b/src/intel/compiler/brw_eu_defines.h
index 8aa2c14fddf..737ea95215b 100644
--- a/src/intel/compiler/brw_eu_defines.h
+++ b/src/intel/compiler/brw_eu_defines.h
@@ -1135,11 +1135,14 @@ tgl_swsb_encode(struct tgl_swsb swsb)
  * tgl_swsb.
  */
 static inline struct tgl_swsb
-tgl_swsb_decode(uint8_t x)
+tgl_swsb_decode(enum opcode opcode, uint8_t x)
 {
    if (x & 0x80) {
       const struct tgl_swsb swsb = { (x & 0x70u) >> 4, x & 0xfu,
-                                     TGL_SBID_DST | TGL_SBID_SET };
+                                     (opcode == BRW_OPCODE_SEND ||
+                                      opcode == BRW_OPCODE_SENDC ||
+                                      opcode == BRW_OPCODE_MATH) ?
+                                     TGL_SBID_SET : TGL_SBID_DST };
       return swsb;
    } else if ((x & 0x70) == 0x20) {
       return tgl_swsb_sbid(TGL_SBID_DST, x & 0xfu);