Mesa (master): intel/tools: Add test for state register as source

[GitLab Mirror]

Module: Mesa
Branch: master
Commit: 0b0e958f4f096863fc29d8acd000caa0f0ff5bc2
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=0b0e958f4f096863fc29d8acd000caa0f0ff5bc2

Author: Sagar Ghuge <sagar.ghuge at intel.com>
Date:   Thu Feb  6 14:39:20 2020 -0800

intel/tools: Add test for state register as source

Signed-off-by: Sagar Ghuge <sagar.ghuge at intel.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3952>

---

 src/intel/tools/tests/gen6/shr.asm      | 1 +
 src/intel/tools/tests/gen6/shr.expected | 1 +
 2 files changed, 2 insertions(+)

diff --git a/src/intel/tools/tests/gen6/shr.asm b/src/intel/tools/tests/gen6/shr.asm
index 3d4d99c78f1..bd9e7c4ff55 100644
--- a/src/intel/tools/tests/gen6/shr.asm
+++ b/src/intel/tools/tests/gen6/shr.asm
@@ -6,3 +6,4 @@ shr(8)          g34<1>UD        g3<0>UD         g1<0>.yUD       { align16 1Q };
 shr(8)          g3<1>.xUD       g3<4>.xUD       0x00000001UD    { align16 1Q };
 shr(8)          g28<1>UD        g3.5<0,1,0>UD   g4.1<0,1,0>UD   { align1 1Q };
 shr(16)         g48<1>UD        g3.5<0,1,0>UD   g4.1<0,1,0>UD   { align1 1H };
+shr(1)          g3<1>D          sr0<0,1,0>D     12D             { align1 1N };
diff --git a/src/intel/tools/tests/gen6/shr.expected b/src/intel/tools/tests/gen6/shr.expected
index 0e218041b16..bfd44f57ca1 100644
--- a/src/intel/tools/tests/gen6/shr.expected
+++ b/src/intel/tools/tests/gen6/shr.expected
@@ -6,3 +6,4 @@
 08 01 60 00 21 0c 61 20 60 00 60 00 01 00 00 00
 08 00 60 00 21 04 80 23 74 00 00 00 84 00 00 00
 08 00 80 00 21 04 00 26 74 00 00 00 84 00 00 00
+08 00 00 00 85 1c 60 20 00 0e 00 00 0c 00 00 00