Mesa (master): iris: Apply the flushes when switching pipelines.
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Wed Feb 26 21:44:49 UTC 2020
Module: Mesa
Branch: master
Commit: a70a605ad63d95a6e7ce7cfd61fc1ca4e9616e74
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a70a605ad63d95a6e7ce7cfd61fc1ca4e9616e74
Author: Rafael Antognolli <rafael.antognolli at intel.com>
Date: Thu Feb 20 11:02:52 2020 -0800
iris: Apply the flushes when switching pipelines.
Even though the workaround description says:
"all the listed commands are non-pipelined and hence flush caused due
to pipeline mode change must not cause performance issues..."
My understanding is that we still need to have the flushes. Also, the
flushes are required not only to stall the pipeline, but also to clear
caches, so I don't think they can simply be discarded.
Additionally, while doing some testing that increased the number of
surface STATE_BASE_ADDRESS emitted, I got a lot more GPU hangs. Adding
these flushes fixes those hangs.
Fixes: b8fbb39a (iris: Implement Gen12 workaround for non pipelined
state)
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3908>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3908>
---
src/gallium/drivers/iris/iris_state.c | 16 ++++------------
1 file changed, 4 insertions(+), 12 deletions(-)
diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c
index 7f25e1f7676..3151c9b62be 100644
--- a/src/gallium/drivers/iris/iris_state.c
+++ b/src/gallium/drivers/iris/iris_state.c
@@ -5047,12 +5047,8 @@ iris_update_surface_base_address(struct iris_batch *batch,
* Workaround the non pipelined state not applying in MEDIA/GPGPU pipeline
* mode by putting the pipeline temporarily in 3D mode..
*/
- if (batch->name == IRIS_BATCH_COMPUTE) {
- iris_emit_cmd(batch, GENX(PIPELINE_SELECT), sel) {
- sel.MaskBits = 3;
- sel.PipelineSelection = _3D;
- }
- }
+ if (batch->name == IRIS_BATCH_COMPUTE)
+ emit_pipeline_select(batch, _3D);
#endif
iris_emit_cmd(batch, GENX(STATE_BASE_ADDRESS), sba) {
@@ -5078,12 +5074,8 @@ iris_update_surface_base_address(struct iris_batch *batch,
*
* Put the pipeline back into compute mode.
*/
- if (batch->name == IRIS_BATCH_COMPUTE) {
- iris_emit_cmd(batch, GENX(PIPELINE_SELECT), sel) {
- sel.MaskBits = 3;
- sel.PipelineSelection = GPGPU;
- }
- }
+ if (batch->name == IRIS_BATCH_COMPUTE)
+ emit_pipeline_select(batch, GPGPU);
#endif
flush_after_state_base_change(batch);
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