Mesa (master): pan/midgard: Don't spill near a branch

[GitLab Mirror]

Module: Mesa
Branch: master
Commit: a0b90b45a9bcef058c8fc6ac88ba5e71a8cedade
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=a0b90b45a9bcef058c8fc6ac88ba5e71a8cedade

Author: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>
Date:   Mon Feb 24 09:36:18 2020 -0500

pan/midgard: Don't spill near a branch

Fixes
dEQP-GLES2.functional.shaders.indexing.varying_array.vec2_dynamic_loop_write_
static_read with register pressure forced down.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso at collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3950>

---

 src/panfrost/midgard/midgard_schedule.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/src/panfrost/midgard/midgard_schedule.c b/src/panfrost/midgard/midgard_schedule.c
index 8dd5ac1d2e2..55fdba0b546 100644
--- a/src/panfrost/midgard/midgard_schedule.c
+++ b/src/panfrost/midgard/midgard_schedule.c
@@ -1054,6 +1054,14 @@ mir_schedule_alu(
                         bundle.control |= stages[i]->unit;
                         bytes_emitted += bytes_for_instruction(stages[i]);
                         bundle.instructions[bundle.instruction_count++] = stages[i];
+
+                        /* If we branch, we can't spill to TLS since the store
+                         * instruction will never get executed. We could try to
+                         * break the bundle but this is probably easier for
+                         * now. */
+
+                        if (branch)
+                                stages[i]->no_spill |= (1 << REG_CLASS_WORK);
                 }
         }