Mesa (master): radeonsi: clean up messy si_emit_rasterizer_prim_state
GitLab Mirror
gitlab-mirror at kemper.freedesktop.org
Wed Jan 8 20:51:04 UTC 2020
Module: Mesa
Branch: master
Commit: fd84e422b6086dc1847b93c852b6de4f1c008394
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=fd84e422b6086dc1847b93c852b6de4f1c008394
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon Jan 6 22:10:04 2020 -0500
radeonsi: clean up messy si_emit_rasterizer_prim_state
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
---
src/gallium/drivers/radeonsi/si_gfx_cs.c | 8 ++--
src/gallium/drivers/radeonsi/si_pipe.h | 4 +-
src/gallium/drivers/radeonsi/si_state.h | 2 +
src/gallium/drivers/radeonsi/si_state_draw.c | 49 ++++++++++---------------
src/gallium/drivers/radeonsi/si_state_shaders.c | 6 +--
5 files changed, 30 insertions(+), 39 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_gfx_cs.c b/src/gallium/drivers/radeonsi/si_gfx_cs.c
index 15f3d238ac5..270304ae9cb 100644
--- a/src/gallium/drivers/radeonsi/si_gfx_cs.c
+++ b/src/gallium/drivers/radeonsi/si_gfx_cs.c
@@ -438,9 +438,6 @@ void si_begin_new_gfx_cs(struct si_context *ctx)
ctx->last_restart_index = SI_RESTART_INDEX_UNKNOWN;
ctx->last_prim = -1;
ctx->last_multi_vgt_param = -1;
- ctx->last_rast_prim = -1;
- ctx->last_flatshade_first = -1;
- ctx->last_sc_line_stipple = ~0;
ctx->last_vs_state = ~0;
ctx->last_ls = NULL;
ctx->last_tcs = NULL;
@@ -492,6 +489,7 @@ void si_begin_new_gfx_cs(struct si_context *ctx)
ctx->tracked_regs.reg_value[SI_TRACKED_PA_SU_HARDWARE_SCREEN_OFFSET] = 0;
ctx->tracked_regs.reg_value[SI_TRACKED_PA_SU_VTX_CNTL] = 0x00000005;
ctx->tracked_regs.reg_value[SI_TRACKED_PA_SC_CLIPRECT_RULE] = 0xffff;
+ ctx->tracked_regs.reg_value[SI_TRACKED_PA_SC_LINE_STIPPLE] = 0;
ctx->tracked_regs.reg_value[SI_TRACKED_VGT_ESGS_RING_ITEMSIZE] = 0x00000000;
ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GSVS_RING_OFFSET_1] = 0x00000000;
ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GSVS_RING_OFFSET_2] = 0x00000000;
@@ -525,11 +523,13 @@ void si_begin_new_gfx_cs(struct si_context *ctx)
ctx->tracked_regs.reg_value[SI_TRACKED_VGT_TF_PARAM] = 0x00000000;
ctx->tracked_regs.reg_value[SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL] = 0x0000001e; /* From GFX8 */
- /* Set all saved registers state to saved. */
+ /* Set all cleared context registers to saved. */
ctx->tracked_regs.reg_saved = 0xffffffffffffffff;
+ ctx->last_gs_out_prim = 0; /* cleared by CLEAR_STATE */
} else {
/* Set all saved registers state to unknown. */
ctx->tracked_regs.reg_saved = 0;
+ ctx->last_gs_out_prim = -1; /* unknown */
}
/* 0xffffffff is a impossible value to register SPI_PS_INPUT_CNTL_n */
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
index 519b0050fd3..06d233e1043 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -1071,10 +1071,8 @@ struct si_context {
int last_restart_index;
int last_prim;
int last_multi_vgt_param;
- int last_rast_prim;
- int last_flatshade_first;
+ int last_gs_out_prim;
int last_binning_enabled;
- unsigned last_sc_line_stipple;
unsigned current_vs_state;
unsigned last_vs_state;
enum pipe_prim_type current_rast_prim; /* primitive type after TES, GS */
diff --git a/src/gallium/drivers/radeonsi/si_state.h b/src/gallium/drivers/radeonsi/si_state.h
index 05f2576b970..0b7881749c8 100644
--- a/src/gallium/drivers/radeonsi/si_state.h
+++ b/src/gallium/drivers/radeonsi/si_state.h
@@ -311,6 +311,8 @@ enum si_tracked_reg {
SI_TRACKED_PA_SC_CLIPRECT_RULE,
+ SI_TRACKED_PA_SC_LINE_STIPPLE,
+
SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
SI_TRACKED_VGT_GSVS_RING_OFFSET_1, /* 3 consecutive registers */
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
index 9702efa68de..e43120cf9ba 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -597,46 +597,37 @@ static void si_emit_rasterizer_prim_state(struct si_context *sctx)
struct radeon_cmdbuf *cs = sctx->gfx_cs;
enum pipe_prim_type rast_prim = sctx->current_rast_prim;
struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
- bool use_ngg = sctx->screen->use_ngg;
+ unsigned initial_cdw = cs->current.cdw;
- if (likely(rast_prim == sctx->last_rast_prim &&
- rs->pa_sc_line_stipple == sctx->last_sc_line_stipple &&
- (!use_ngg ||
- rs->flatshade_first == sctx->last_flatshade_first)))
- return;
-
- if (util_prim_is_lines(rast_prim)) {
+ if (unlikely(si_is_line_stipple_enabled(sctx))) {
/* For lines, reset the stipple pattern at each primitive. Otherwise,
* reset the stipple pattern at each packet (line strips, line loops).
*/
- radeon_set_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
- rs->pa_sc_line_stipple |
- S_028A0C_AUTO_RESET_CNTL(rast_prim == PIPE_PRIM_LINES ? 1 : 2));
- sctx->context_roll = true;
+ unsigned value = rs->pa_sc_line_stipple |
+ S_028A0C_AUTO_RESET_CNTL(rast_prim == PIPE_PRIM_LINES ? 1 : 2);
+
+ radeon_opt_set_context_reg(sctx, R_028A0C_PA_SC_LINE_STIPPLE,
+ SI_TRACKED_PA_SC_LINE_STIPPLE, value);
}
- unsigned gs_out = si_conv_prim_to_gs_out(sctx->current_rast_prim);
+ unsigned gs_out_prim = si_conv_prim_to_gs_out(rast_prim);
+ if (unlikely(gs_out_prim != sctx->last_gs_out_prim &&
+ (sctx->ngg || sctx->gs_shader.cso))) {
+ radeon_set_context_reg(cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out_prim);
+ sctx->last_gs_out_prim = gs_out_prim;
+ }
- if (rast_prim != sctx->last_rast_prim &&
- (sctx->ngg || sctx->gs_shader.cso)) {
- radeon_set_context_reg(cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out);
+ if (initial_cdw != cs->current.cdw)
sctx->context_roll = true;
- if (use_ngg) {
- sctx->current_vs_state &= C_VS_STATE_OUTPRIM;
- sctx->current_vs_state |= S_VS_STATE_OUTPRIM(gs_out);
- }
- }
+ if (sctx->ngg) {
+ unsigned vtx_index = rs->flatshade_first ? 0 : gs_out_prim;
- if (use_ngg) {
- unsigned vtx_index = rs->flatshade_first ? 0 : gs_out;
- sctx->current_vs_state &= C_VS_STATE_PROVOKING_VTX_INDEX;
- sctx->current_vs_state |= S_VS_STATE_PROVOKING_VTX_INDEX(vtx_index);
+ sctx->current_vs_state &= C_VS_STATE_OUTPRIM &
+ C_VS_STATE_PROVOKING_VTX_INDEX;
+ sctx->current_vs_state |= S_VS_STATE_OUTPRIM(gs_out_prim) |
+ S_VS_STATE_PROVOKING_VTX_INDEX(vtx_index);
}
-
- sctx->last_rast_prim = rast_prim;
- sctx->last_sc_line_stipple = rs->pa_sc_line_stipple;
- sctx->last_flatshade_first = rs->flatshade_first;
}
static void si_emit_vs_state(struct si_context *sctx,
diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c
index c5412f3b143..151085b781a 100644
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -3050,7 +3050,7 @@ bool si_update_ngg(struct si_context *sctx)
sctx->flags |= SI_CONTEXT_VGT_FLUSH;
sctx->ngg = new_ngg;
- sctx->last_rast_prim = -1; /* reset this so that it gets updated */
+ sctx->last_gs_out_prim = -1; /* reset this so that it gets updated */
return true;
}
return false;
@@ -3073,7 +3073,7 @@ static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
sctx->ia_multi_vgt_param_key.u.uses_gs = sel != NULL;
si_update_common_shader_state(sctx);
- sctx->last_rast_prim = -1; /* reset this so that it gets updated */
+ sctx->last_gs_out_prim = -1; /* reset this so that it gets updated */
ngg_changed = si_update_ngg(sctx);
if (ngg_changed || enable_changed)
@@ -3127,7 +3127,7 @@ static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
si_update_tess_uses_prim_id(sctx);
si_update_common_shader_state(sctx);
- sctx->last_rast_prim = -1; /* reset this so that it gets updated */
+ sctx->last_gs_out_prim = -1; /* reset this so that it gets updated */
bool ngg_changed = si_update_ngg(sctx);
if (ngg_changed || enable_changed)
More information about the mesa-commit
mailing list