Mesa (master): iris: Implement Gen12 workaround for non pipelined state

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Module: Mesa
Branch: master
Commit: b8fbb39ab2c962e38f6c9d668de57582faf39b70
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=b8fbb39ab2c962e38f6c9d668de57582faf39b70

Author: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Date:   Mon Jan 13 17:50:06 2020 +0200

iris: Implement Gen12 workaround for non pipelined state

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3365>

---

 src/gallium/drivers/iris/iris_state.c | 39 +++++++++++++++++++++++++++++++++++
 1 file changed, 39 insertions(+)

diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c
index a0917761ac6..67d9f758ef7 100644
--- a/src/gallium/drivers/iris/iris_state.c
+++ b/src/gallium/drivers/iris/iris_state.c
@@ -1014,12 +1014,24 @@ iris_init_compute_context(struct iris_batch *batch)
 {
    UNUSED const struct gen_device_info *devinfo = &batch->screen->devinfo;
 
+   /* GEN:BUG:1607854226:
+    *
+    *  Start with pipeline in 3D mode to set the STATE_BASE_ADDRESS.
+    */
+#if GEN_GEN == 12
+   emit_pipeline_select(batch, _3D);
+#else
    emit_pipeline_select(batch, GPGPU);
+#endif
 
    iris_emit_default_l3_config(batch, devinfo, true);
 
    init_state_base_address(batch);
 
+#if GEN_GEN == 12
+   emit_pipeline_select(batch, GPGPU);
+#endif
+
 #if GEN_GEN == 9
    if (devinfo->is_geminilake)
       init_glk_barrier_mode(batch, GLK_BARRIER_MODE_GPGPU);
@@ -5030,6 +5042,20 @@ iris_update_surface_base_address(struct iris_batch *batch,
 
    flush_before_state_base_change(batch);
 
+#if GEN_GEN == 12
+   /* GEN:BUG:1607854226:
+    *
+    *  Workaround the non pipelined state not applying in MEDIA/GPGPU pipeline
+    *  mode by putting the pipeline temporarily in 3D mode..
+    */
+   if (batch->name == IRIS_BATCH_COMPUTE) {
+      iris_emit_cmd(batch, GENX(PIPELINE_SELECT), sel) {
+         sel.MaskBits = 3;
+         sel.PipelineSelection = _3D;
+      }
+   }
+#endif
+
    iris_emit_cmd(batch, GENX(STATE_BASE_ADDRESS), sba) {
       sba.SurfaceStateBaseAddressModifyEnable = true;
       sba.SurfaceStateBaseAddress = ro_bo(binder->bo, 0);
@@ -5048,6 +5074,19 @@ iris_update_surface_base_address(struct iris_batch *batch,
 #endif
    }
 
+#if GEN_GEN == 12
+   /* GEN:BUG:1607854226:
+    *
+    *  Put the pipeline back into compute mode.
+    */
+   if (batch->name == IRIS_BATCH_COMPUTE) {
+      iris_emit_cmd(batch, GENX(PIPELINE_SELECT), sel) {
+         sel.MaskBits = 3;
+         sel.PipelineSelection = GPGPU;
+      }
+   }
+#endif
+
    flush_after_state_base_change(batch);
 
    batch->last_surface_base_address = binder->bo->gtt_offset;